Table 373. Icipr0–Icipr2 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface
36.5.1.4 Internal Channel Interrupt Pending Registers 0–2 (ICIPR0–ICIPR2)
The interrupt channel register to channel association is described in
Offset 0x014–0x01C
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 332. Internal Channel Interrupt Pending Registers (ICIPR0–ICIPR2)
Field
0–31
EOC_CH[x]
Parameter num_intch vector has positional inference for registers ICIPR0–2, such that:
•
num_intch(i) (i = 0–31) corresponds to ICIPR0 bit[0:31].
•
num_intch(i) (i = 32–63) corresponds to ICIPR1 bit[0:31].
•
num_intch(i) (i = 64–95) corresponds to ICIPR2 bit[0:31].
If any num_intch(i) value is '0', corresponding bit is not implemented and read access
returns '0' on that bit location. Thus:
•
If num_intch[31:0] is all 0's, register ICIPR0 is not implemented.
•
If num_intch[63:32] is all 0's, register ICIPR1 is not implemented.
•
If num_intch[95:64] is all 0's, register ICIPR2 is not implemented.
In any or all of the above circumstances, the corresponding registers are treated as
reserved space and any attempt to access this space generates a transfer error.
36.5.1.5 Interrupt Mask Register (IMR)
The description of the Interrupt Mask Register is given below.
774/2058
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0
Table 373. ICIPR0–ICIPR2 field descriptions
End of conversion interrupt pending bit for channel x
0 End of conversion for CH[x] has not occurred.
1 End of conversion for CH[x] has occurred.
Table 374. ICIPR0–2 Registers to channel association
Register
ICIPR0
ICIPR1
ICIPR2
DocID027809 Rev 4
6 7 8 9
EOC_CH[x]
w1c
0 0 0 0
22 23 24 25
EOC_CH[x]
w1c
0 0 0 0
Description
Table 374.
Access: User Read Only
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
Register bits 31:0
EOC_CH[31:0]
EOC_CH[63:32]
EOC_CH[95:64]
14 15
0 0
30 31
0 0