Clock Generation Module (MC_CGM)
Table 267. Auxiliary Clock 11 Select Status Register (CGM_AC11_SS) field descriptions
Field
0–3
Reserved
Auxiliary Clock 11 Source Selection Status — This value indicates the current source for auxiliary
clock 11.
0000 IRCOSC
0001 XOSC
0010 PLL0 PHI
0011 PLL0 PHI1
0100 reserved
0101 reserved
4–7
0110 reserved
0111 reserved
SELSTAT
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
8–31
Reserved
24.3.1.36 Auxiliary Clock 11 Divider 0 Configuration Register (CGM_AC11_DC0)
Address 0x0968
0
1
2
R
0
0
DE
W
Reset
0
0
0
16
17
18
R
0
0
0
W
Reset
0
0
0
Figure 216. Auxiliary Clock 11 Divider 0 Configuration Register (CGM_AC11_DC0)
This register controls auxiliary clock 11 divider 0. See
divider characteristics.
Note:
Byte and half-word write accesses are not allowed for this register. Such accesses do not
result in an exception, but the value is not loaded with the new value.
528/2058
Access: User read/write, Supervisor read/write, Test read/write
3
4
5
6
0
0
0
0
19
20
21
22
0
0
0
0
0
0
0
0
DocID027809 Rev 4
Description
7
8
9
10
DIV
0
0
0
0
23
24
25
26
0
0
0
0
0
0
0
0
Section 24.4.3.2: Fractional Divider Details
RM0400
11
12
13
14
0
0
0
0
27
28
29
30
0
0
0
DIV_FMT
0
0
0
0
for
15
0
31
0
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