Decorated Storage Memory Controller (Dsmc) - STMicroelectronics SPC572L series Reference Manual

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Decorated Storage Memory Controller (DSMC)

30.1 Introduction
This section details hardware support for atomic read-modify-write memory operations. In
the Power Architecture, these capabilities are called "decorated storage". It is supported by
capabilities in the processor cores plus instantiations of a Decorated Storage Memory
Controller (DSMC).
The Decorated Storage APU defines instructions for providing load and store operations to
memory addresses that require additional semantics beyond just the reading and writing of
data values to the addressed memory locations. Decorated storage operations are intended
to be used for specific devices or memory targets that require these additional semantics. A
"decoration" is the additional semantic information to be applied to the decorated storage
operation by the DSMC.
Consider the basic mnemonics, syntax and formats for the decorated load instructions.
For loads, the syntax is l[b,h,w]d{cb}x rT,rB,rA where the data size specifier is
defined as 8-bit (b = byte), 16-bit (h = halfword) or 32-bit (w = word), and the three register
specifiers include rT as the destination target register, rB as the effective address and rA
as the decoration. The optional {cb} specifier defines a version of the instruction which is
treated as a cache bypass operation.
The syntax for store instruction is st[b,h,w]d{cb}x rS,rB,rA where the same data
size specifiers are used, and the three register specifiers are rS as the source data register,
rB as the effective address and rA as the decoration. The cache bypass attribute is again
specified with the use of the optional {cb} in the instruction mnemonic.
For all decorated loads and stores, the memory effective address is simply defined by the rB
register (hence the "x" mnemonic suffix, signaling an "indexed" addressing mode) and the
decoration is specified by the rA register. The core transmits the contents of the rA register
as the decoration value along with the access address (register rB) to the DSMC.
The decorated load and store instruction formats are shown in
0 1 2 3
lbdx 0 1 1 1 1 1
lhdx 0 1 1 1 1 1
lwdx 0 1 1 1 1 1
lbdcbx 0 1 1 1 1 1
lhdcbx 0 1 1 1 1 1
lwdcbx 0 1 1 1 1 1
0 1 2 3
stbdx 0 1 1 1 1 1
sthdx 0 1 1 1 1 1
stwdx 0 1 1 1 1 1
stbdcbx 0 1 1 1 1 1
sthdcbx 0 1 1 1 1 1
stwdcbx 0 1 1 1 1 1
Figure 274. Power Architecture Decorated Load and Store Instruction Formats
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rT
rT
rT
rT
rT
rT
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rS
rS
rS
rS
rS
rS
Decorated Storage Memory Controller (DSMC)
rA rB
rA rB
rA rB
rA rB
rA rB
rA rB
rA rB
rA rB
rA rB
rA rB
rA rB
rA rB
DocID027809 Rev 4
Figure 274.
1 0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 0 0 1 1
1 0 0 1 0 0 0 0 1 1
1 0 0 0 0 0 0 0 1 0
1 0 0 0 1 0 0 0 1 0
1 0 0 1 0 0 0 0 1 0
1 0 1 0 0 0 0 0 1 1
1 0 1 0 1 0 0 0 1 1
1 0 1 1 0 0 0 0 1 1
1 0 1 0 0 0 0 0 1 0
1 0 1 0 1 0 0 0 1 0
1 0 1 1 0 0 0 0 1 0
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