Figure 374. Filter Configuration Paths (Fir Or 1X4Poles Iir) - STMicroelectronics SPC572L series Reference Manual

RM0400
x(n) Register
FIR Section
37.4.6.1 Rounding
The Decimation Filter performs rounding operations in two different locations, as shown in
Figure 374:
• to obtain the filter output result with 16 bits
•
to obtain the IIR feedback result to be stored in tap4 registers with 24 bits
The rounding mechanism implements the Convergent Rounding methodology (also known
as round-to-nearest even number), which makes the decision on rounding up or down
based on the value of the lower portion of data to be rounded (LS_WORD). The rounding
up/down condition is equal to the traditional rounding except when the LS_WORD has the
format {1000...00}. In this particular case, the rounding procedure is like the example of
Figure 375. If the MS_WORD is odd, the value is rounded up. Otherwise the value is
rounded down.

Figure 374. Filter Configuration Paths (FIR or 1x4Poles IIR)

Coefficient 0
-1
Z
Tap0 Coefficient 1
-1
Z
Tap1 Coefficient 2
-1
Z
Tap2 Coefficient 3
-1
Z
Tap3 Coefficient 4
DocID027809 Rev 4
+ +
Scale Factor S
Coefficient 5
Coefficient 6
Coefficient 7
Coefficient 8
Decimation Filter
By-
00
Round/Sat
IIR
Round/Sat
FI
01 10
B
FTYPE[1:0]
-1
Z
Tap4
-1
Z
IIR Section
Tap5
-1
Z
Tap6
-1
Z
Tap7
A y(n)
831/2058
841