Features - STMicroelectronics SPC572L series Reference Manual

Decimation Filter
37.1.2

Features

The Decimation Filter block includes these distinctive features:
•
Selectable 4th order IIR filter, or an 8th order FIR filter
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–
–
–
–
–
–
•
Input and output buffers with DMA capability
• Slave-bus interface to device
•
Filter taps access for debug
• Filter initialization (flush) and stabilization (prefill) commands
•
Decimation controlled by an internal counter
• Integrator unit accumulates filter output values, signaled or absolute, with 32-bit
resolution. The integrator can be controlled by software or hardware signals.
37.1.3 Modes of operation
This section describes the operation modes of the Decimation Filter. The modes are
selected using the following DECFILTER_MCR register fields: MDIS, FREN, FRZ, ISEL
(see Section 37.3.2.1: Decimation Filter Module Configuration Register
(DECFILTER_MCR)").
The mode selection is summarized in
1. Freeze mode can also be activated from outside the Decimation Filter, depending on the MCU, if FREN=1.
37.1.3.1 Standalone mode
In this case, the data is provided by the central processor using the device slave-bus
interface or DMA interface signals. Once the data is filtered the decimated result is available
806/2058
Input/output with 16-bit (fixed point) two's complement signed values
Internal taps with 16-bit (feed-forward portion of first IIR) and 24-bit (feedback
portion) resolutions (fixed point) for two's complement signed value
24-bit programmable filter coefficients (fixed point) for two's complement signed
value
MAC unit with 51-bit fixed point accumulator
Convergent rounding methodology
Two's complement overflow or saturation selection
58 clock cycles to process the input
Table 418. Operation Mode Selection
Mode
Standalone
(1)
Freeze
Low Power
Reserved
DocID027809 Rev 4
Table 418
MDIS FREN, FRZ
0
0
1
All other combinations
RM0400
ISEL
(0, 0)
or
(0, 1)
or
(1, 0)
1, 1
X
1
X
X