State Logic Unit (Slu) - STMicroelectronics SPC572L series Reference Manual

RM0400
CPU exception vector
0x0000
0x0010
0x0020
0x0030
0x0040
0x0050
0x0060
0x0061
0x0062
0x0070
0x0080
0x0090
0x00A0
0x00B0
0xVVVV , low two bits = 01
3
0xVVVV , low two bits = 01
3
63.6.3

State logic unit (SLU)

Complex triggers and system performance monitor functions are implemented in the SLU.
The SPU creates debug events based upon states in a sequence. A sequence can consist
of a single state, or any number of states up to 8. Each state consists of combinational logic
allowing AND/OR operations on inputs from the trigger source unit. Single or multiple (up to
8) actions can be triggered by a state machine.
A logic diagram of one SLU state is shown in
Table 1040. Processor exception processing conditions
CnPEVP register
CPUn field value
0x0000
0x1000
0x2000
0x3000
0x4000
0x5000
0x6000
0x6100
0x6200
0x7000
0x8000
0x9000
0xA000
0xB000
0xVVVV , high two bits =
3
01
0xVVVV , high two bits =
3
01
DocID027809 Rev 4
Sequence Processing Unit (SPU)
Exception condition
Critical Input—autovectored
Machine check
Data storage
Instruction storage
External input—autovectored
Alignment
Program trap
Program illegal
Program privileged
Performance monitor
System call
Debug
EFPU data exception
EFPU round exception
External input—vectored
Critical input—vectored
Figure 1098.
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