Table 53. Boot Header Structure - STMicroelectronics SPC572L series Reference Manual

Device configuration
The first header found that contains the value 005Ah in the first half-word is valid for booting.
The whole header structure is shown in
Address offset
Offset 00h
0 1
0
16 17 18
0
The memory area of the BAF is protected from execution for functional safety
considerations. This is achieved by disabling BAF execution in PFLASH control register3
(PFLASHC_PFCR3[BAF_DIS]). Finally a mode change (from DRUN to DRUN again) is
requested from Mode Entry module to activate the new core configuration and make the
cores jump to their respective reset vectors. At this point the BAF has finished its operation.
6.7.9.3 LINFlexD_0 and M_CAN_1 pin configuration
Table 54
Reset
Pads
Function
PA[10] GPIO
Input buffer off
Output buffer off
PA[11] GPIO
Input buffer off
Output buffer off
172/2058

Table 53. Boot header structure

00h
04h
08h
0Ch
10h
14h
2 3 4 5
0
19 20 21
0
Figure 17. Boot header configuration
shows the device pin configurations for LINFlexD_0 and M_CAN_1 modules.
Table 54. M_CAN_1 and LINFlexD_0 pin configuration
Initial Serial Boot Mode
Function
M_CAN_1 Tx
LINFlexD_0 Rx
and
M_CAN_1 Rx
DocID027809 Rev 4
Table 53.
Boot Header Configuration (see
6 7 8 9
5
22 23 24 25
0
Serial Boot Mode
after a valid CAN
message received
Pad
Configuration
Output:—
Push/Pull
medium drive
no pullup/pulldown
Input:—
pull-up
hysteresis
TTL voltage level
Contents
Figure
Boot Core Reset Vector
Reserved
Reserved
Reserved
Reserved
10 11 12 13
26 27 28 29
Serial Boot Mode
LINFlexD message
Function
M_CAN_1 Tx LINFlexD_0 Tx
M_CAN_1 Rx LINFlexD_0 Rx
RM0400
17)
14 15
A
30 31
0
after a valid
received
Function