Microcontroller Initialization - STMicroelectronics SPC572L series Reference Manual

Fast Ethernet Controller (FEC)
The following registers require initialization:
•
EIMR
•
EIR (clear by writing FFFF_FFFFh)
•
TFWR (optional)
•
IALR / IAUR
•
GAUR / GALR
•
PALR / PAUR (only needed for full duplex flow control)
•
OPD (only needed for full duplex flow control)
•
RCR
• TCR
•
MSCR (optional)
• MIB_RAM (clear)
•
FRSR (optional)
• EMRBR
•
ERDSR
• ETDSR
•
Transmit Descriptor ring (empty)
• Receive Descriptor ring (empty)
48.5.6

Microcontroller initialization

In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is
asserted. After the microcontroller initialization sequence is complete, hardware is ready for
operation.
The sequence is as follows:
1. Initialize the backoff random number seed.
2. Activate receiver.
3. Activate transmitter.
4. Clear transmit FIFO.
5. Clear receive FIFO.
6. Initialize the transmit ring pointer.
7. Initialize the receive ring pointer.
8. Initialize FIFO count registers.
48.5.7 User initialization (after setting ECR[ETHER_EN])
After setting ECR[ETHER_EN], you can set up the buffer/frame descriptors and write to
TDAR and RDAR. See
48.5.8 Network interface options
The FEC supports an MII and reduced MII interface for 10/100 Mbps Ethernet, as well as a
7-wire serial interface for 10 Mbps Ethernet. The RCR[MII_MODE] and RCR[RMII_MODE]
bits select the interface mode. In MII mode (RCR[MII_MODE] = 1 and
RCR[RMII_MODE] = 0), there are 18 signals defined by the IEEE 802.3 standard and
supported by the EMAC.
1346/2058
Section 48.5.3: Buffer
Table 784 shows these signals.
DocID027809 Rev 4
descriptors, for more details.
RM0400