Core E200Z215An3 Description; Overview Of The E200Z215An3 Core - STMicroelectronics SPC572L series Reference Manual

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Core e200z215An3 description

12.1

Overview of the e200z215An3 core

The e200z215An3 is a single-issue 32-bit PowerISA 2.06 VLE compliant design with 32-bit
general-purpose registers (GPRs). The e200z215An3 core implements the VLE (variable-
length encoding) ISA, providing improved code density. The VLE ISA is further documented
in PowerISA 2.06, a separate document.
An Embedded Floating-point (EFPU2) APU is provided to support real-time single-precision
floating-point embedded numerics operations using the general-purpose registers.
The EFPU2 APU supports 32-bit IEEE-754 single-precision floating-point formats and
operates in a pipelined fashion. The 32-bitgeneral-purpose register file is used for source
and destination operands. There is a unified storage model for scalar single-precision
floating-point data types of 32-bits and the normal integer type. Low latency floating-point
add, subtract, mixed add/subtract, sum, diff, min, max, multiply, multiply-add, multiply-sub,
divide, square root, compare, and conversion operations are provided. Most operations
can be pipelined.
A Lightweight Signal Processing Extension (LSP) APU is provided to support real-time
SIMD fixed-point embedded numerics operations using the general-purpose registers. All
arithmetic instructions that execute in the core operate on data in the general purpose
registers (GPRs). The GPRs support register pairing in order to support vector instructions
defined by the LSP APU. These instructions operate on a vector pair of 16-bit or 32-bit
data types, and deliver vector and scalar results. A wide variety of data manipulation,
multiply, multiply/accumulate, and dot product instructions along with specialized memory
access instructions allow a sustained throughput of up to 16 × 16-bit multiply/accumulate
operation per cycle.
The e200z215An3 processor integrates an integer execution unit, a branch control unit,
instruction fetch unit, load/store unit, and a multi-ported register file capable of sustaining
three read and two write operations per clock cycle. Most integer instructions execute in a
single clock cycle. Branch target prefetching is performed by the branch unit to allow single-
cycle branches in many cases.
e200z215An3 contains a Nexus Class 3+ real-time debug module with support for program
and data trace features as well as extensive trace controls.
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