Functional Description - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
DMA Channel Enable.
Enables the DMA channel
0
0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMUX. The
ENBL
DMA has separate channel enables/disables, which should be used to disable or reconfigure a
DMA channel.
1 DMA channel is enabled.
DMA Channel Trigger Enable .
Enables the periodic trigger capability for the triggered DMA Channel.
1
0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route
TRIG
the specified source to the DMA channel. (Normal mode)
1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger
mode.
DMA Channel Source (Slot)
2–7
SOURCE
Specifies which DMA source, if any, is routed to a particular DMA channel. See your device's chip
configuration details for information about the peripherals and their slot numbers.
20.4

Functional description

The primary purpose of the DMAMUX is to provide flexibility in the system's use of the
available DMA channels. As such, configuration of the DMAMUX is intended to be a static
procedure done during execution of the system boot code. However, if the procedure
outlined in
the DMAMUX may be changed during the normal operation of the system.
Functionally, the DMAMUX channels may be divided into two classes:
•
Channels that implement the normal routing functionality plus periodic triggering
capability
•
Channels that implement only the normal routing functionality
20.4.1 DMA channels with periodic triggering capability
Besides the normal routing functionality, the first channels of the DMAMUX provide a
special periodic triggering capability that can be used to provide an automatic mechanism to
transmit bytes, frames, or packets at fixed intervals without the need for processor
intervention. The trigger is generated by the periodic interrupt timer (PIT); as such, the
configuration of the periodic triggering interval is done via configuration registers in the PIT.
See the section on periodic interrupt timer for more information on this topic.
Note: Because of the dynamic nature of the system (due to DMA channel priorities, bus
arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a
trigger and the actual DMA transfer cannot be guaranteed.
Table 207. DMAMUX_CHCFGn field descriptions
Section 20.5.2, Enabling and configuring sources
DocID027809 Rev 4
Direct Memory Access Multiplexer (DMAMUX)
Description
is followed, the configuration of
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