Features Summary - STMicroelectronics SPC572L series Reference Manual

RM0400
2.2

Features summary

On-chip modules within SPC572Lx include the following features:
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1 main CPU, single issue, 32-bit CPU core complex (e200z2)
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1568 KB (1536 KB code flash + 32 KB data flash) on-chip flash memory
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64 KB general-purpose data SRAM
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System Memory Protection Unit (SMPU)
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16-channel Direct Memory Access controllers (eDMA) with two channel multiplexer for
up to 60 DMA sources
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Interrupt Controller (INTC) supporting up to 1024 interrupt sources (all are not
assigned)
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System Timer Module (STM)
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2 Software Watchdog Timers (SWT)
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One Periodic Interrupt Timer (PIT) instance with four standard 32-bit timer channels
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One Periodic Interrupt Timer (PIT) instance with two 32-bit timer channels which can be
combined into one 64-bit channel
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Single phase-locked loop with stable clock domain for peripherals and core (PLL)
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Single crossbar switch architecture for concurrent access to peripherals, flash memory,
or SRAM from multiple bus masters
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System Integration Unit Lite (SIUL2)
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Boot Assist Flash (BAF) supports factory programming using a serial bootload through
the UART Serial Boot Mode Protocol (physical interface (PHY) can be e.g., UART and
CAN )
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PASS module (supporting 256-bit JTAG password protection)
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Device life cycle monitoring
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Generic Timer Module (GTM101)
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Enhanced analog-to-digital converter system with:
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Decimation unit to support SD ADC data conditioning
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1 Deserial Serial Peripheral Interface (DSPI) module
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2 LIN and UART communication interfaces (LINFlexD) modules
• 1 microsecond-bus channel (composed of one DSPI and one LINFlexD)
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4 SENT (Single Edge Nibble Transmission) channels
• 2 Modular Controller Area Network (M_CAN) modules
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1 Clock Calibration on CAN Unit (CCCU)
Power Architecture embedded specification compliance
Instruction set enhancement allowing variable length encoding (VLE), encoding a
mix of 16-bit and 32-bit instructions, for code size footprint reduction
Single-precision floating point operations
Saturation Instructions Extension adding scalar saturating arithmetic support to
the PowerISA Integer Saturation (ISAT).
Supporting multiple blocks allowing EEPROM emulation
RWW between data EEPROM and code flash memory
Three 12-bit SAR analog converters
One 16-bit Sigma-Delta analog converter
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