External Signal Description - STMicroelectronics SPC572L series Reference Manual

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in the Output Buffer register. The filter output is also consumed by a CPU or DMA mastering
the same device slave-bus interface. This operation mode can be used to debug the filter
stability or to decimate data in System RAM.
37.1.3.2 Low Power mode
Low power mode corresponds to the module disable mode or stop mode. In the module
disable mode the filter input is disabled and it is not possible to enter Freeze mode. The
system clock is stopped. And in stop mode, the system clock is also stopped.
37.1.3.3 Freeze mode
This mode is also known as debug mode. All filter action is frozen, either through software
or by the hardware SoC debug request signal. If a freeze request comes when the filter is
processing an input, it enters freeze mode only after the processing finishes.
37.2

External signal description

Note: The Decimation Filter does not provide metastability protection or filtering for these signals.
37.2.1 Integrator enable signal
This signal is used to enable the hardware integrator. For more details, see
Section 37.4.13.4: Integrator enabling and
37.2.2 Integrator halt signal
This signal is used to halt the hardware integrator. For more details, see
Integrator enabling and
37.2.3 Integrator reset signal
This signal is used to reset the hardware integrator. For more details, see
Integrator
37.2.4 Integrator output request signal
This signal is used to update the integrator output result. For more details, see
Section 37.4.13.2: Integrator
37.3 Memory map and register definition
This section provides the memory maps and detailed descriptions of all registers. Accesses
to reserved areas of the memory map can return a bus error, depending on the device
integration.
This module communicates with the slave-bus line that is related to the device integration.
Below the memory map is described.
halting.
reset.
outputs.
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halting.
Decimation Filter
Section 37.4.13.4:
Section 37.4.13.3:
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