Figure 586. Dspi Clock And Transfer Attributes Register (In Master Mode) (Dspi_Ctarn) - STMicroelectronics SPC572L series Reference Manual

RM0400
46.3.3 DSPI Clock and Transfer Attributes Register (In Master Mode)
(DSPI_CTARn)
CTARs are used to define different transfer attributes:
•
In master mode, the CTARs define combinations of transfer attributes such as frame
size, clock phase and polarity, data bit ordering, baud rate, and various delays.
•
In slave mode, a subset of the bitfields in CTAR0 and CTAR1 set the slave transfer
attributes.
Do not write to the CTARs while the DSPI is in the Running state.
When the DSPI is configured as:
•
SPI master – the CTAS field in the command portion of the TX FIFO entry selects
which CTAR is used.
•
SPI bus slave – the CTAR0 register is used.
•
DSI master – the DSICTAS field in the DSPI DSI Configuration Register 0 (DSICR0)
selects which CTAR is used.
•
DSI bus slave – the CTAR1 register is used.
In CSI Configuration, the transfer attributes are based on whether the current frame is:
•
SPI data – follow the protocol described for SPI Configuration,
•
DSI data – follow the protocol described for DSI Configuration.
CSI Configuration is valid only in master mode.
TSB mode sets some limitations on transfer attributes:
•
Clock phase is forced to be CPHA = 1 and the CPHA bit setting has no effect.
•
PCS lines are driven at the driving edge of the SCK clock together with SOUT, so PCS
assertion and negation delays control is unavailable and PCSSCK, PASC, CSSCK and
ASC fields have no effect.
•
Delay after transfer can be set from 1 to 64 serial clocks via PDT and DT fields.
Address: Base + 0x000C
0 1
R
DBR
W
Reset 0 1
16 17
R
CSSCK
W
Reset 0 0

Figure 586. DSPI Clock and Transfer Attributes Register (In Master Mode) (DSPI_CTARn)

2 3 4 5
FMSZ
1 1 1 0
18 19 20 21
ASC
0 0 0 0
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
6 7 8 9
PCSSCK
0 0 0 0
22 23 24 25
DT
0 0 0 0
Access: User read/write
10 11 12 13
PASC PDT
0 0 0 0
26 27 28 29
BR
0 0 0 0
14 15
PBR
0 0
30 31
0 0
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