Table 907. Res_Vd10 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
to be generated when the selected voltage passes the trigger event. These bits are loaded
from the flash during the boot sequence.
Offset: PMC_BASE + 0x00A8
0 1
R 0 0
W
Reset 0 0
16 17
R
W
Reset 0 0
Field
0–15 Reserved.
LVD10_F reset enable—LVD on the Flash supply.
16
RES_VD10[LVD10_F] selects functional or destructive reset.
LVD10_F
0 Disabled.
1 Enabled.
LVD10_C reset enable—LVD on the Core supply.
17
RES_VD10[LVD10_C] selects functional or destructive reset.
LVD10_C
0 Disabled.
1 Enabled.
18 Reserved.
LVD10_IF reset disable—LVD on the Ethernet supply.
19
RES_VD10[LVD10_IF] selects functional or destructive reset.
LVD10_IF
0 Disabled.
1 Enabled.
LVD10_IJ reset enable—LVD on the JTAG supply.
20
RES_VD10[LVD10_IJ] selects functional or destructive reset.
LVD10_IJ
0 Disabled.
1 Enabled.
21–31 Reserved.
54.3.1.12 Event Pending register (EPR_VD14)
This Event Pending register indicates the present and past state of the voltage detect
signals. If the voltage detect event crosses the trigger threshold after the last clearing event,
the flag bit is set asynchronously. Write '1' to clear the flag.
Power Management Controller digital interface (PMC_dig)
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0
0 0 0 0
Figure 945. Reset Event Select register (RES_VD10)

Table 907. RES_VD10 field descriptions

DocID027809 Rev 4
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Description
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
0 0 0 0
14 15
0 0
0 0
30 31
0 0
0 0
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