Debug Port Enable/Disable - STMicroelectronics SPC572L series Reference Manual

Flash Memory Programming and Configuration
1. First write 0b00 to the PASS_CHSEL[GRP] register field to indicate registers controlled
by password 0 are to be unlocked.
2. Write the 256-bit value for password 0 to the set of eight 32-bit password challenge
input registers (PASS_CINn) beginning with PASS_CIN0. The password must be
written as a sequence of eight 32-bit writes, with the most significant bits of the
password written to PASS CIN0.
3. Write a 0 to PASS_LOCK3_PG0[RL3] bit and verify a successful write.
4. Repeat the above steps for password 1.
The result of a successful sequence is that the blocks associated with the unlocked read
lock group can be read by a debugger.
31.5

Debug port enable/disable

The mechanism for temporarily enabling the SPC572Lx debug port after it has been locked
by its life cycle state is similar to the flash memory read protection mechanism detailed in
Section 31.4: Secure read
field is used instead of the RP0–RP4 fields.
31.6 Implementing OTP
Any flash block within the flash array can be assigned, at any time, to be OTP. OTP means
that flash erase of the entire block is disabled and only 64-bit double words that are already
erased (i.e., flash content is 0xFFFF_FFFF_FFFF_FFFF) can be programmed. Over-
programming is not possible.
Flash blocks are assigned as OTP by writing a DCF record. The block becomes OTP after
the next reset.
Warning:
This capability resides within the Tamper Detection Module (TDM). The records are detailed
in Table 71: DCF client list
the entries for the OTP_EN0, OTP_EN1, OTP_EN2, and OTP_EN3 DCF records in the
Tamper Detect section of the table.
31.7 Implementing test mode disable
The SPC572Lx flash memory module includes a mechanism to disable manufacturer entry
into test mode. Extreme care must be taken when using this feature, as blocks that are
selected to be protected in this method are able to have possible failures analyzed by
manufacturer's failure analysts.
Test mode disable prevents all high voltage operations to the flash executed by the internal
state-machine, as well as reads through the state machine, and reads through the Array
Integrity state machine when using test mode interfaces.
670/2058
protection. The difference is that the PASS_LOCK3_PGn[DBL]
After a flash block is configured as OTP, it cannot be changed
back.
in Chapter 8: Device Configuration Format (DCF)
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RM0400
Records. See