Table 329. Erm_Cr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Error Reporting Module (ERM)
Field
Enable Memory 0 Single Correction Interrupt Notification
This field is initialized by hardware reset.
0
0 Interrupt notification of Memory 0 single-bit correction events is disabled.
ESCIE0
1 Interrupt notification of Memory 0 single-bit correction events is enabled.
Refer to the device configuration chapter for details on Memory 0 mapping.
Enable Memory 0 Non-Correctable Interrupt Notification
This field is initialized by hardware reset.
1
0 Interrupt notification of Memory 0 non-correctable error events is disabled.
ENCIE0
1 Interrupt notification of Memory 0 non-correctable error events is enabled.
Refer to the device configuration chapter for details on Memory 0 mapping.
Enable Memory 1 Single Correction Interrupt Notification
This field is initialized by hardware reset.
4
0 Interrupt notification of Memory 1 single-bit correction events is disabled.
ESCIE1
1 Interrupt notification of Memory 1 single-bit correction events is enabled.
Refer to the device configuration chapter for details on Memory 1 mapping.
Enable Memory 1 Non-Correctable Interrupt Notification
This field is initialized by hardware reset.
5
0 Interrupt notification of Memory 1 non-correctable error events is disabled.
ENCIE1
1 Interrupt notification of Memory 1 non-correctable error events is enabled.
Refer to the device configuration chapter for details on Memory 1 mapping.
Enable Memory 2 Single Correction Interrupt Notification
This field is initialized by hardware reset.
8
0 Interrupt notification of Memory 2 single-bit correction events is disabled.
ESCIE2
1 Interrupt notification of Memory 2 single-bit correction events is enabled.
Refer to the device configuration chapter for details on Memory 2 mapping.
Enable Memory 2 Non-Correctable Interrupt Notification
This field is initialized by hardware reset.
9
0 Interrupt notification of Memory 2 non-correctable error events is disabled.
ENCIE2
1 Interrupt notification of Memory 2 non-correctable error events is enabled.
Refer to the device configuration chapter for details on Memory 2 mapping.
Enable Memory 3 Single Correction Interrupt Notification
This field is initialized by hardware reset.
12
0 Interrupt notification of Memory 3 single-bit correction events is disabled.
ESCIE3
1 Interrupt notification of Memory 3 single-bit correction events is enabled.
Refer to the device configuration chapter for details on Memory 3 mapping.
Enable Memory 3 Non-Correctable Interrupt Notification
This field is initialized by hardware reset.
13
0 Interrupt notification of Memory 3 non-correctable error events is disabled.
ENCIE3
1 Interrupt notification of Memory 3 non-correctable error events is enabled.
Refer to the device configuration chapter for details on Memory 3 mapping.
Enable Memory 4 Single Correction Interrupt Notification
This field is initialized by hardware reset.
16
0 Interrupt notification of Memory 4 single-bit correction events is disabled.
ESCIE4
1 Interrupt notification of Memory 4 single-bit correction events is enabled.
Refer to the device configuration chapter for details on Memory 4 mapping.
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Table 329. ERM_CR field descriptions

DocID027809 Rev 4
Description
RM0400