Table 1021. L2Nsel2 Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Sequence Processing Unit (SPU)
Table 1020. L2nSEL1 register field descriptions(Continued)
Field
29–24
SecondANDInput4
31–30
63.5.1.2.3 Level2 Mux state n selection 2 (L2nSEL2)
Figure 1079
0x19 (State0)
0x1D (State1)
0x21 (State2)
0x25 (State3)
Offset
0x29 (State4)
0x2D (State5)
0x31 (State6)
0x35 (State7)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0
ThirdANDInput4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The L2nSEL2 register fields are described in
Field
Third AND Gate Input1 Selection.
000000No Input is selected (tie to 1'b1)
000001Level1 MUX 0 output
5–0
000010Level1 MUX 1 output
ThirdANDInput1 000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
7–6 Reserved. Read returns 0.
1834/2058
Second AND Gate Input 4 Selection.
000001Level1 MUX 0 output
000010Level1 MUX 1 output
000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
Reserved. Read returns 0.
shows the format of the L2nSEL2 register where the state number, n = 0–7.
0 0
ThirdANDInput3
Figure 1079. L2nSEL2 register format

Table 1021. L2nSEL2 register field descriptions

DocID027809 Rev 4
Description
0 0
ThirdANDInput2
Table 1021.
Description
RM0400
Access: User read/write
8 7 6 5 4 3 2 1
0 0
ThirdANDInput1
0