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56.3.2.15 Peripheral Status Register 0 (ME_PS0)
Address 0x060
0
1
2
R
W
Reset
0
0
0
16
17
18
R
0
0
0
W
Reset
0
0
0
This register provides the status of the peripherals. Please refer to
56.3.2.16 Peripheral Status Register 1 (ME_PS1)
Address 0x064
0
1
2
R
0
0
0
W
Reset
0
0
0
16
17
18
R
0
0
0
W
Reset
0
0
0
This register provides the status of the peripherals. Please refer to
3
4
5
6
0
0
0
0
0
0
0
0
19
20
21
22
0
0
0
0
0
0
Figure 972. Peripheral Status Register 0 (ME_PS0)
3
4
5
6
0
0
0
0
0
0
19
20
21
22
0
0
0
0
0
0
0
0
Figure 973. Peripheral Status Register 1 (ME_PS1)
DocID027809 Rev 4
Access: User read, Supervisor read, Test read
7
8
9
10
0
0
0
0
0
0
0
0
23
24
25
26
0
0
0
0
0
0
0
0
Access: User read, Supervisor read, Test read
7
8
9
10
0
0
0
0
0
0
0
0
23
24
25
26
0
0
0
0
0
0
0
0
Mode Entry Module (MC_ME)
11
12
13
14
0
0
0
0
0
0
27
28
29
30
0
0
0
0
0
0
Table 929
for details.
11
12
13
14
0
0
0
0
0
0
27
28
29
30
0
0
0
0
0
Table 929
for details.
15
0
0
0
0
31
0
0
0
0
15
0
0
0
0
31
0
0
0
0
1621/2058
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