Table 369. Saradc Digital Interface Register Map - STMicroelectronics SPC572L series Reference Manual

RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter-
Note: The actual availability and number of registers and their configuration are chip-specific. For
this information, see "Device Configuration" chapter.
Offset
0x000 Main Configuration Register (MCR)
0x004 Main Status Register (MSR)
0x008–0x00C
0x010 Interrupt Status Register (ISR)
0x014–0x01C Internal channel Interrupt Pending Registers 0–2 (ICIPR0–ICIPR2)
0x020 Interrupt Mask Register (IMR)
0x024–0x02C Internal Channel Interrupt Mask Registers 0–2 (ICIMR0–ICIMR2)
0x030 Watchdog Threshold Interrupt Status Register (WTISR)
0x034 Watchdog Threshold Interrupt Mask Register (WTIMR)
0x038–0x03C
0x040 DMA Enable Register (DMAE)
0x044–0x04C Internal Channel DMA Select Registers 0–2 (ICDSR0–ICDSR2)
0x050–0x05C
0x060–0x06C Watchdog Threshold Registers 0–3 (WTHRHLR0–WTHRHLR3)
0x070–0x090
0x094–0x0A0 Conversion Timing Registers 0–3 (CTR0–3)
Internal Channel Normal Conversion Mask Registers 0–2
0x0A4–0x0AC
(ICNCMR0–ICNCMR2)
0x0B0
Internal Channel Injected Conversion Mask Registers 0–2
0x0B4–0x0BC
(ICJCMR0–ICJCMR2)
0x0C0–0x0C4
0x0C8 Power Down Exit Delay Register (PDEDR)

Table 369. SARADC digital interface register map

Register
DocID027809 Rev 4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register
Location
classification
(1)
36.5.1.1 on
Saf-Relv
page 769
36.5.1.2 on
No-Saf
page 771
36.5.1.3 on
No-Saf
page 773
36.5.1.4 on
Saf-Relv
page 774
36.5.1.5 on
Saf-Relv
page 774
36.5.1.6 on
Saf-Relv
page 775
36.5.1.7 on
Saf-Relv
page 776
36.5.1.8 on
Saf-Relv
page 777
36.5.1.9 on
Saf-Relv
page 778
36.5.1.10 on
Saf-Relv
page 779
36.5.1.11 on
Saf-Relv
page 780
36.5.1.12 on
Saf-Relv
page 781
36.5.1.13 on
Saf-Relv
page 781
36.5.1.14 on
Saf-Relv
page 782
36.5.1.15 on
Saf-Relv
page 784
767/2058
803