Table 216. Lfast And Ethernet Use Cases - STMicroelectronics SPC572L series Reference Manual

RM0400
If SPC572Lx is operated as LFAST slave the reference clock coming from the LFAST
master is fed as an external clock signal (EXTAL bypass) to be used by the PLL0 as clock
input.
If SPC572Lx is operated as LFAST master the reference clock is selectable by "AUX Clock
Selector 1" and provided to the external LFAST slave by the DRCLK pin.
Figure 164
connections to the DRCLK pin.
PLL0:PHI1
DRCLK
(PA[6])
21.6.1.1 LFAST and Ethernet use cases
On SPC572Lx, LFAST and Ethernet are not used simultaneously and this leads to two
different use-cases for the clock tree configuration, as shown in
Use
case
(1)
1 800 MHz
1280 MH
(2)
2
z
1. In this use case the maximum achievable baud rate for the LINFlexD is 25 MHz, if LIN_CLK is configured for 100 MHz.
2. In this use case the maximum achievable baud rate for the LINFlexD is 20 MHz.
shows the clock routing for the LFAST module on the device, including
Figure 164. Device LFAST clocking
XOSC
PLL0:PHI

Table 216. LFAST and Ethernet use cases

80 MHz 100 MHz 80 MHz
80 MHz — 80 MHz
DocID027809 Rev 4
RF_REF
÷ 1...128
40 MHz 80 MHz
40 MHz 80 MHz
Clocking
Interprocessor
Bus LFAST
Table 216.
80 MHz not
or 100 Hz running
320 MHz
80 MHz
(4 phases
)
50 MHz
not
running
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