STMicroelectronics STM32F427 Manual
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STMicroelectronics STM32F427 Manual

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See also: Reference Manual
STM32F427/437 and STM32F429/439 line limitations
Silicon identification
This errata sheet applies to the revision A and Y of STMicroelectronics STM32F427/437
and STM32F429/439 microcontroller lines.
The STM32F42xx and STM32F43xx devices feature an ARM
FPU, for which an errata notice is also available (see
The full list of part numbers is shown in
Table
1:
•
by the revision code marked below the order code on the device package
•
by the last three digits of the Internal order code printed on the box label
STM32F427xx, STM32F429xx
STM32F437xx, STM32F439xx
1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the RM0090
STM32F4xx reference manual for details on how to find the revision code).
2. Refer to
the date code on the different packages.
Reference
STM32F427xx
STM32F437xx
STM32F429xx
STM32F439xx
September 2013
STM32F42xx and STM32F43xx

Table 1. Device identification

Order code
Appendix A: Revision code on device marking
STM32F427VG, STM32F427ZG, STM32F427IG, STM32F427VI, STM32F427ZI,
STM32F427II
STM32F437VG, STM32F437ZG, STM32F437IG, STM32F437VI, STM32F437ZI,
STM32F437II
STM32F429VG, STM32F429ZG, STM32F429IG, STM32F429VI, STM32F429ZI,
STM32F429II, STM32F429BG, STM32F429BI, STM32F429NI, STM32F429NG
STM32F439VI, STM32F439VG, STM32F439ZG, STM32F439ZI, STM32F439IG,
STM32F439II, STM32F439BG, STM32F439BI, STM32F439NI, STM32F439NG
DocID023833 Rev 5
Section 1
Table
2. The products are identifiable as shown in
Revision code marked on device
for details on how to identify the revision code and

Table 2. Device summary

Part number
Errata sheet
®
32-bit Cortex™-M4 core with
for details).
(1)
"A" and "Y"
(2)
1/36
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  • Page 1: Table 1. Device Identification

    STM32F42xx and STM32F43xx Errata sheet STM32F427/437 and STM32F429/439 line limitations Silicon identification This errata sheet applies to the revision A and Y of STMicroelectronics STM32F427/437 and STM32F429/439 microcontroller lines. ® The STM32F42xx and STM32F43xx devices feature an ARM 32-bit Cortex™-M4 core with...

  • Page 2: Table Of Contents

    Contents STM32F42xx and STM32F43xx Contents ARM 32-bit Cortex-M4 with FPU limitations ..... . 7 Cortex-M4 interrupted loads to stack pointer can cause erroneous behavior .
  • Page 3 STM32F42xx and STM32F43xx Contents 2.5.5 nRTS signal abnormally driven low after a protocol violation ..17 OTG_FS peripheral limitations ....... . . 17 2.6.1 Data in RxFIFO is overwritten when all channels are disabled simultaneously .
  • Page 4 Contents STM32F42xx and STM32F43xx 2.11.2 DMA request not automatically cleared by DMAEN=0 ... . . 27 Appendix A Revision code on device marking ......29 Revision history .
  • Page 5 STM32F42xx and STM32F43xx List of tables List of tables Table 1. Device identification ............1 Table 2.
  • Page 6 List of figures STM32F42xx and STM32F43xx List of figures Figure 1. TFBGA216 top package view ..........29 Figure 2.

  • Page 7: Arm 32-Bit Cortex-M4 With Fpu Limitations

    STM32F42xx and STM32F43xx ARM 32-bit Cortex-M4 with FPU limitations ARM 32-bit Cortex-M4 with FPU limitations An errata notice of the STM32F42xx and STM32F43xx core is available from the following web address: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b_errata_01/index.html. All the described limitations are minor and related to the revision r0p1-v1 of the CortexM4 core.

  • Page 8: Stm32F42Xx And Stm32F43Xx Silicon Limitations

    STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations Table 4 gives quick references to all documented limitations. Legend for Table 4: A = workaround available; N = no workaround available; P = partial workaround available, ‘-’ and grayed = fixed. Table 4.
  • Page 9 STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations Table 4. Summary of silicon limitations (continued) Links to silicon limitations Revision A Revision Y Section 2.5.1: Idle frame is not detected if receiver clock speed is deviated Section 2.5.2: In full duplex mode, the Parity Error (PE) flag can be cleared by writing to the data register Section 2.5: USART Section 2.5.3: Parity Error (PE) flag is not set when...

  • Page 10: System Limitations

    STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx Table 4. Summary of silicon limitations (continued) Links to silicon limitations Revision A Revision Y Section 2.9.1: SDIO HW flow control Section 2.9.2: Wrong CCRCFAIL status after a response without CRC is received Section 2.9.3: Data corruption in SDIO clock dephasing Section 2.9: SDIO (NEGEDGE) mode...

  • Page 11: Wakeup Sequence From Standby Mode When Using More Than

    STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations BX lr } 2.1.3 Wakeup sequence from Standby mode when using more than one wakeup source Description The various wakeup sources are logically OR-ed in front of the rising-edge detector which generates the wakeup flag (WUF). The WUF needs to be cleared prior to Standby mode entry, otherwise the MCU wakes up immediately.

  • Page 12: Mpu Attribute To Rtc And Iwdg Registers Could Be Managed

    STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx 2.1.5 MPU attribute to RTC and IWDG registers could be managed incorrectly Description If the MPU is used and the non bufferable attribute is set to the RTC or IWDG memory map region, the CPU access to the RTC or IWDG registers could be treated as bufferable, provided that there is no APB prescaler configured (AHB/APB prescaler is equal to 1).

  • Page 13: Over-Drive And Under-Drive Modes Unavailability

    STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations 2.1.8 Over-drive and Under-drive modes unavailability Description The Over-drive and Under-drive modes are not available on revision A devices. Workaround None. This limitation is fixed in silicon revision Y. IWDG peripheral limitation 2.2.1 RVU and PVU flags are not reset in STOP mode Description...

  • Page 14: Start Cannot Be Generated After A Misplaced Stop

    STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx 2.3.2 Start cannot be generated after a misplaced Stop Description If a master generates a misplaced Stop on the bus (bus error), the peripheral cannot generate a Start anymore. Workaround In the I²C standard, it is allowed to send a Stop only at the end of the full byte (8 bits + acknowledge), so this scenario is not allowed.

  • Page 15: Higher Than ((Vdd+0.3) / 0.7) V

    STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations Workaround If the master device allows it, use the clock stretching mechanism by programming the bit NOSTRETCH=0 in the I2C_CR1 register. If the master device does not allow it, ensure that the software is fast enough when polling the TXE or ADDR flag to immediately write to the DR data register.

  • Page 16: Usart Peripheral Limitations

    STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx USART peripheral limitations 2.5.1 Idle frame is not detected if receiver clock speed is deviated Description If the USART receives an idle frame followed by a character, and the clock of the transmitter device is faster than the USART receiver clock, the USART receive signal falls too early when receiving the character start bit, with the result that the idle frame is not detected (IDLE flag is not set).

  • Page 17: Break Frame Is Transmitted Regardless Of Ncts Input Line Status

    STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations 2.5.4 Break frame is transmitted regardless of nCTS input line status Description When CTS hardware flow control is enabled (CTSE = 1) and the Send Break bit (SBK) is set, the transmitter sends a break frame at the end of the current transmission regardless of nCTS input line status.

  • Page 18: Otg Host Blocks The Receive Channel When Receiving In Packets And No

    STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx Workaround Use one of the following recommendations: Configure the RxFIFO to host a minimum of 2 × MPSIZ + 2 × data status entries. The application has to check the RXFLVL bit (RxFIFO non-empty) in the OTG_FS_GINTSTS register before disabling each IN channel.

  • Page 19: Ethernet Peripheral Limitations

    STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations Ethernet peripheral limitations 2.7.1 Incorrect layer 3 (L3) checksum is inserted in transmitted IPv6 packets without TCP, UDP or ICMP payloads Description The application provides the per-frame control to instruct the MAC to insert the L3 checksums for TCP, UDP and ICMP packets.

  • Page 20: Transmit Frame Data Corruption

    STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx However, if the TxFIFO read controller receives the TxFIFO flush command exactly one clock cycle after receiving the status from the MAC, the controller remains stuck in the Idle state and stops transmitting frames from the TxFIFO. The system can recover from this state only with a reset (e.g.
  • Page 21 STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations Table 5. Impacted registers and bits Register name Bit number Bit name DMA registers ETH_DMABMR EDFE DTCEFD ETH_DMAOMR FUGF GMAC registers CSTF 19:17 ETH_MACCR IPCO APCS ETH_MACFFR MAC frame filter register ETH_MACHTHR 31:0 Hash Table High Register ETH_MACHTLR...
  • Page 22 STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx Table 5. Impacted registers and bits (continued) Register name Bit number Bit name VLANTC ETH_MACVLANTR 15:0 VLANTI ETH_MACRWUFFR all remote wakeup registers WFFRPR ETH_MACPMTCSR ETH_MACA0HR MAC address 0 high register ETH_MACA0LR MAC address 0 low register ETH_MACA1HR MAC address 1 high register ETH_MACA1LR...

  • Page 23: Fmc Peripheral Limitation

    STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations Workaround Two workarounds could be applicable: • Ensure a delay of four TX_CLK/RX_CLK clock cycles between the successive write operations to the same register. • Make several successive write operations without delay, then read the register when all the operations are complete, and finally reprogram it after a delay of four TX_CLK/RX_CLK clock cycles.

  • Page 24: Corruption Of Data Read From The Fmc

    STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx 2.8.4 Corruption of data read from the FMC Description When the FMC is used as stack, heap or variable data, an interrupt occurring during a CPU read access to the FMC may results in read data corruption or hard fault exception. This problem does not occur when read accesses are performed by another master or when FMC accesses are done when the interrupts are disabled.

  • Page 25: Fmc Dynamic And Static Banks Switching

    STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations This limitation will be fixed in next silicon revision. 2.8.7 FMC dynamic and static banks switching Description The dynamic and static banks cannot be accessed concurrently. Workaround Do not use dynamic and static banks at the same time. The SDRAM device must be in self- refresh before switching to the static memory mapped on the NOR/PSRAM or NAND/PC- Card controller.

  • Page 26: Data Corruption In Sdio Clock Dephasing (Negedge) Mode

    STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx 2.9.3 Data corruption in SDIO clock dephasing (NEGEDGE) mode Description When NEGEDGE bit is set to ‘1’, it may lead to invalid data and command response read. Workaround None. A configuration with the NEGEDGE bit equal to ‘1’ should not be used. 2.9.4 CE-ATA multiple write command and card busy signal management Description...

  • Page 27: Adc Peripheral Limitations

    STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations 2.10 ADC peripheral limitations 2.10.1 ADC sequencer modification during conversion Description If an ADC conversion is started by software (writing the SWSTART bit), and if the ADC_SQRx or ADC_JSQRx registers are modified during the conversion, the current conversion is reset and the ADC does not restart a new conversion sequence automatically.
  • Page 28 STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx Workaround To stop the current DMA-to-DAC transfer and restart, the following sequence should be applied: Check if DMAUDR is set. Clear the DAC/DMAEN bit. Clear the EN bit of the DAC DMA/Stream Reconfigure by software the DAC, DMA, triggers etc.

  • Page 29: Figure 1. Tfbga216 Top Package View

    STM32F42xx and STM32F43xx Revision code on device marking Appendix A Revision code on device marking Figure Figure Figure Figure 4 Figure Figure Figure 7 show the marking compositions for the TFBGA216, WLCSP143, LQFP208, UFBGA176, LQFP176, LQFP144 and LQFP100 packages, respectively.The only fields shown are the Additional field containing the revision code and the Year and Week fields making up the date code.

  • Page 30: Figure 2. Wlcsp143 Top Package View

    Revision code on device marking STM32F42xx and STM32F43xx Figure 2. WLCSP143 top package view Year Week Date code = Year+Week Additional information field including Revision code MS32786V1 Figure 3. LQFP208 top package view 30/36 DocID023833 Rev 5...

  • Page 31: Figure 4. Ufbga176 Top Package View

    STM32F42xx and STM32F43xx Revision code on device marking Figure 4. UFBGA176 top package view DocID023833 Rev 5 31/36...

  • Page 32: Figure 5. Lqfp176 Top Package View

    Revision code on device marking STM32F42xx and STM32F43xx Figure 5. LQFP176 top package view 32/36 DocID023833 Rev 5...

  • Page 33: Figure 6. Lqfp144 Top Package View

    STM32F42xx and STM32F43xx Revision code on device marking Figure 6. LQFP144 top package view DocID023833 Rev 5 33/36...

  • Page 34: Figure 7. Lqfp100 Top Package View

    Revision code on device marking STM32F42xx and STM32F43xx Figure 7. LQFP100 top package view 34/36 DocID023833 Rev 5...

  • Page 35: Table 6. Document Revision History

    STM32F42xx and STM32F43xx Revision history Revision history Table 6. Document revision history Date Revision Changes 11-Feb-2013 Initial release. Document converted to new template. 25-Feb-2013 Added Section 2.8.4: Corruption of data read from the FMC Added Silicon revision Y. Removed the reference to ‘Cortex-M4F’ in the whole document. Updated Section 2.8.1: Dummy read cycles inserted when reading synchronous...

  • Page 36: Docid023833 Rev 5

    Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

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