Table 851. Dmarxe Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
50.4.2.26 DMA Rx Enable Register (DMARXE)
This register enables the DMA RX interface. This register can be written and read by
software any time.
Address (GCR address)
:
0 1
R 0 0
W
Reset 0 0
16 17
R
W
Reset 0 0
1
Depends on no_of_filters. Refer to device configuration chapter to see the number of filters used in the
device.
Field
Reserved
0 –
Read returns 0.
(2**RX_CH_NU
M–1)
Note: Refer to the device configuration chapter for the value of RX_CH_NUM used in this device.
DMA Rx channel Y enable
0 DMA Rx channel Y disabled
1 DMA Rx channel Y enabled
(2**RX_CH_NU
M) – 31
DRE[2**RX_CH
Note: The actual size of the register DMARXE depends on the value of the static parameter
(1)
_NUM–1:0]
Note: Refer to the device configuration chapter for the value of RX_CH_NUM used in this device.
1. ** stands for exponentiation.
1
+10h
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
Figure 870. DMA Rx Enable Register (DMARXE)

Table 851. DMARXE field descriptions

RX_CH_NUM. When DMARXE = 0x00000000, the DMA RX interface FSM is forced (soft
reset) in Idle state.
DocID027809 Rev 4
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
DRE
0 0 0 0
Description
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
LINFlexD
14 15
0 0
0 0
30 31
0 0
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