Register Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Address offset
024h INTC Interrupt Acknowledge Register for Processor 1 (INTC_IACKR1)
028h INTC Interrupt Acknowledge Register for Processor 2 (INTC_IACKR2)
02Ch INTC Interrupt Acknowledge Register for Processor 3 (INTC_IACKR3)
030h
034h
038h
03Ch
040h–05Fh
060h–85Eh
860h-FFC
Note: A transfer error will be asserted if an access is attempted outside of the memory map or for
any unimplemented registers. For example, if the design has only 512 interrupt sources and
a source > 512 is accessed, a transfer error is asserted.
18.5.2

Register descriptions

With the exception of the INTC_SSCIRn and INTC_PSRn registers, all of the registers are
32-bit. Any combination of accessing the four bytes of a register with a single access is
supported, provided that the access does not cross a register boundary. These supported
accesses include types and sizes of 8 bits, aligned 16 bits, misaligned 16 bits to the middle
two bytes, and aligned 32 bits.
Although INTC_SSCIRn are 8 bits wide and INTC_PSRn are 16 bits wide, they can be
accessed with a single 16-bit or 32-bit access, provided that the access does not cross a 32-
bit boundary.
Some registers have specific exceptions to these rules, as outlined in their definitions.
In software vector mode, the effects of a read of the INTC Interrupt Acknowledge register
(INTC_IACKRn) are the same regardless of the size of the read. In either software or
hardware vector mode, the size of a write to the INTC end-of-interrupt register
(INTC_EOIRn) does not affect the operation of the write.
18.5.2.1 INTC Block Configuration Register (INTC_BCR)
The Block Configuration Register is used to configure options of the INTC.
Table 154. INTC memory map(Continued)
INTC End Of Interrupt Register for Processor 0 (INTC_EOIR0)
INTC End Of Interrupt Register for Processor 1 (INTC_EOIR1)
INTC End Of Interrupt Register for Processor 2 (INTC_EOIR2)
INTC End Of Interrupt Register for Processor 3 (INTC_EOIR3)
INTC Software Set/Clear Interrupt Register 0 (INTC_SSCIR0)–
INTC Software Set/Clear Interrupt Register 31(INTC_SSCIR31)
INTC Priority Select Registers (INTC_PSR0 – INTC_PSR1023)
DocID027809 Rev 4
Register
Reserved
Interrupt Controller (INTC)
Location
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