Special Purpose Register (Spr) Summary - STMicroelectronics SPC572L series Reference Manual

RM0400
1. The levels that determine these bits are set by the factory and may change between revisions of the
device.
Core: p_cpuid[0:7] = 0x00
2. Undefined on POR assertion, unchanged on external PORESET assertion
3. Reset by processor reset external PORESET if DBCR0[EDM] = 0, as well as unconditionally by POR
4. Read-only registers
6.2.2

Special purpose register (SPR) summary

PowerISA 2.06 and implementation-specific SPRs for the e200z215An3 core are listed in
Table 13. All registers are 32 bits in size. Register bits are numbered from bit 0 to bit 31
(most-significant to least-significant). An SPR may be read or written with the mfspr and
mtspr instructions. In the instruction syntax, compilers should recognize the mnemonic
name given in
Mnemonic
XER Integer Exception Register
LR Link Register
CTR Count Register
SRR0 Save/Restore Register 0
SRR1 Save/Restore Register 1
PID0 Process ID Register
CSRR0 Critical Save/Restore Register 0
CSRR1 Critical Save/Restore Register 1
DEAR Data Exception Address Register
Table 12. Reset settings for e200z215An3 resources(Continued)
Resource
PID0
PIR
4
PVR
SPEFSCR
SPRG0
SPRG1
SPRG2
SPRG3
SRR0
SRR1
4
SVR
XER
Table 13.
Table 13. Special purpose registers
Name
DocID027809 Rev 4
System reset setting
0x0000_0000
0x0000_00 || p_cpuid[0:7]
—
0x0000_0000
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
—
0x0000_0000
SPR
Access
number
1 R/W
8 R/W
9 R/W
26 R/W
27 R/W
48 R/W
58 R/W
59 R/W
61 R/W
Device configuration
1
2
2
2
2
2
2
e200z
Privileged
specific
No No
No No
No No
Yes No
Yes No
Yes No
Yes No
Yes No
Yes No
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