Trap Debug Event - STMicroelectronics SPC572L series Reference Manual

RM0400
57.2.3 Linked Instruction Address Compare and Data Address Compare
events
Data Address Compare 1, 2, 3, and 4 debug events may be 'linked' with an Instruction
Address Compare event by setting the DAC[1–4]LNK control bits in DBCR2 and DBCR8 to
further refine when a Data Address Compare debug event is generated. DAC1 may be
linked with IAC1, DAC2 (when not used as a mask or range bounds register) may be linked
with IAC3. DAC3 may be linked with IAC5, DAC4 (when not used as a mask or range
bounds register) may be linked with IAC7. When linked, a DAC debug event occurs when
the same instruction that generates the DAC 'hit' also generates a corresponding linked IAC
'hit'. When linked, the IAC event is not recorded in the Debug Status register, regardless of
whether a corresponding linked DAC event occurs, or whether the IAC event enable is set.
When enabled and execution of a load or store class instruction results in a data access
with an address that meets the criteria specified in the DBCRx, DACx, and DVCx Registers,
and the instruction also meets the criteria for generating an Instruction Address Compare
event, a Linked Data Address Compare debug event occurs. This event can occur and be
recorded in DBSR regardless of the setting of MSR
DBSR is used for recording these events. The IAC status bit is not set if the corresponding
Instruction Address Compare register is linked.
Linking is enabled using control bits in DBCR2 and DBCR8. Note that linking is only
available in EDM or IDM. Attempts to use linking otherwise are ignored.
Note: Linked DAC events will not be recorded if a load multiple word or store multiple word type
instruction is interrupted prior to completion by a critical input or external input interrupt.
57.2.4

Trap debug event

A Trap debug event (TRAP) occurs if Trap debug events are enabled (DBCR0
Trap instruction (tw) is executed, and the conditions specified by the instruction for the trap
are met. This event can occur and be recorded in DBSR regardless of the setting of MSR
When a Trap debug event occurs, the DBSR
exception.
57.2.5 Branch Taken debug event
A Branch Taken debug event (BRT) occurs if Branch Taken debug events are enabled
(DBCR0
BRT
an unconditional branch, or a conditional branch whose branch condition is true), and
MSR =1. Branch Taken debug events are not recognized if MSR
DE
execution of the branch instruction and thus DBSR
debug event. When a Branch Taken debug event is recognized, the DBSR
to record the debug exception, and the address of the branch instruction will be recorded in
DSRR0.
57.2.6 Instruction Complete debug event
An Instruction Complete debug event (ICMP) occurs if Instruction Complete debug events
are enabled (DBCR0
execution of an instruction is suppressed due to the instruction causing some other
exception that is enabled to generate an interrupt, then the attempted execution of that
instruction does not cause an Instruction Complete debug event. The se_sc instruction
does not fall into the category of an instruction whose execution is suppressed, since the
=1) and execution is attempted of a branch instruction that will be taken (either
=1), execution of any instruction is completed, and MSR
ICMP
DocID027809 Rev 4
e200z215An3 Core Debug Support
. The normal DAC1 status bit in the
DE
bit is set to 1 to record the debug
TRAP
can not be set by a Branch Taken
IDE
=1), a
TRAP
=0 at the time of
DE
bit is set to 1
BRT
=1. If
DE
1653/2058
.
DE
1719