Continuous Serial Communications Clock - STMicroelectronics SPC572L series Reference Manual

Deserial Serial Peripheral Interface (DSPI)
While masking the delays, the software must follow the following masking rules, else correct
operation is not guaranteed.
•
MASC bit masks the "After SCK" delay for the current frame.
•
MCSC bit masks the "PCS to SCK" delay for the next frame.
•
"After SCK" (t
in the continuous selection format.
• The "PCS to SCK" delay for the first frame in the continuous selection format cannot be
masked.
•
Masking of only t
•
Masking of both t
frames is equal to half the baud rate set by the user software.
•
Masking of only t
the t
the baud rate.
•
The user software must not mask these delays if the continuous selection format is not
used and MCR[FCPCS] is asserted.
•
Rules applicable to the Continuous Selection Format are applicable here, too.
Figure 629
frames are transferred with both t
terminated the transfer. The last frame has t
In case any chip select is to be changed, then the fast continuous selection format should be
terminated and then the chips selects should change and appropriate delays must be
introduced.
46.5.7

Continuous Serial Communications Clock

The DSPI provides the option of generating a continuous SCK signal for slave peripherals
that require a continuous clock.
Continuous SCK is enabled by setting the CONT_SCKE bit in the MCR. Enabling this bit
generates the Continuous SCK only if MCR[HALT] bit is low. Continuous SCK is valid in all
configurations.
Continuous SCK is only supported for CPHA = 1. Clearing CPHA is ignored if the
CONT_SCKE bit is set. Continuous SCK is supported for Modified Transfer Format.
1202/2058
) delay must not be masked when the current frame is the last frame
ASC
is not allowed. If t
ASC
and t
ASC
is allowed. In this case, the delay between two frames is equal to
CSC
time and thus the user software must ensure that the t
ASC
shows the timing for a Fast Continuous Selection Format transfer. Here seven
Figure 629. Example of Fast Continuous Selection Format
DocID027809 Rev 4
is masked then t
ASC
delays is allowed. In this case, the delay between two
CSC
and t delays masked except for the last frame that
ASC CSC
delay at its end.
ASC
RM0400
must be masked too.
CSC
time is greater than
ASC