Table 942. Dbcr4 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
Bit Name
0 — Reserved
Data Value Compare 1 Control. DVC1C controls whether DVC1 data value comparisons
utilize the normal compare operation, or an alternate "inverted compare" operation. In
inverted polarity mode, data value compares perform a not-equal comparison. See details in
1 DVC1C
the DBCR2 register definition.
0 Normal DVC1 operation.
1 Inverted polarity DVC1 operation
2 — Reserved
Data Value Compare 2 Control. DVC2C controls whether DVC2 data value comparisons
utilize the normal compare operation, or an alternate "inverted compare" operation. In
inverted polarity mode, data value compares perform a not-equal comparison. See details in
3 DVC2C
the DBCR2 register definition
0 Normal DVC2 operation.
1 Inverted polarity DVC2 operation
4:12 — Reserved
Data Address Compare 1 Extended Mask Control High. DAC1XMH extends the range of the
DAC1XM field
13 DAC1XMH
0 DAC1XM masks 0–15 low-order address bits
1 DAC1XM masks 16–31 low-order address bits
14 — Reserved
Data Address Compare 2 Extended Mask Control High. DAC2XMH extends the range of the
DAC2XM field.
15 DAC2XMH
0 DAC2XM masks 0–15 low-order address bits
1 DAC2XM masks 16–31 low-order address bits
Data Address Compare 1 Extended Mask Control. DAC1XM allows for binary power of 2
address range compares for DAC1 without requiring the use of DAC2.
Value of DAC1XMH || DAC1XM:
16:19 DAC1XM
00000
00001–11111
Data Address Compare 2 Extended Mask Control
Value of DAC2XMH || DAC2XM:
00000
00001–11111
20:23 DAC2XM
DAC2XM allows for binary power of 2 address range compares for DAC2.
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Table 942. DBCR4 field descriptions

No additional masking when DBCR2[DAC12M] = 00
Exact Match Bit Mask. One to 31 low-order bits are masked in DAC1 when
comparing the storage address with the value in DAC1 for exact address compare
(DBCR2[DAC12M] = 00). Address ranges of 2 bytes to 2GB are supported.
No additional masking when DBCR2[DAC12M] = 00
Exact Match Bit Mask. One to 31 low-order bits are masked in DAC2 when
comparing the storage address with the value in DAC2 for exact address compare
(DBCR2[DAC12M] = 00). Address ranges of 2 bytes to 2GB are supported.
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