Table 669. Lcr Field Description - STMicroelectronics SPC572L series Reference Manual

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
47.6.2.14 LVDS Control Register (LCR)
:
Offset 0040h
0 1
R 0 0
W
Reset 0 0
16 17
R
W
Reset 0 1
1
Set by user software and cleared by system hardware.
Field
0-7 Reserved
SW signal to take LVDS LD out of Sleep mode. This bit can be changed only when DRFEN is high.
8
0 No effect
SWWKLD
1 LVDS LD will be taken out of sleep (provided no other source is trying to put it in sleep)
SW signal to put LVDS LD into Sleep mode. This bit can be changed only when DRFEN is high.
9
0 No effect
SWSLPLD
1 LVDS LD will be put in sleep
SW signal to take LVDS LR out of Sleep mode. This bit can be changed only when DRFEN is high.
10
0 No effect
SWWKLR
1 LVDS LR will be taken out of sleep (provided no other source is trying to put it in sleep)
SW signal to put LVDS LR into Sleep mode. This bit can be changed only when DRFEN is high.
11
0 No effect
SWSLPLR
1 LVDS LR will be put in sleep (provided no other source is trying to wake it up)
SW signal to turn OFF the LVDS LD. This bit can be changed only when DRFEN is high.
12
0 No effect
SWOFFLD
1 LVDS LD will be turned OFF(provided no other source is trying to turn the LD ON)
SW signal to turn ON the LVDS LD. This bit can be changed only when DRFEN is high.
13
0 No effect
SWONLD
1 LVDS LD will be turned ON
SW signal to turn OFF the LVDS LR. This bit can be changed only when DRFEN is high.
14
0 No effect
SWOFFLR
1 LVDS LR will be turned OFF (provided no other source is trying to turn the LR ON)
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21 22
0
0 1 0 0
Figure 654. LVDS Control Register (LCR)

Table 669. LCR field description

6 7 8 9
0 0
0 0 0 0
23 24 25
0 0 0 0
0 0 0 0
Description
DocID027809 Rev 4
Access: User read/write
10 11 12 13
0 0 0 0
26 27 28 29
1 0 0 1
14 15
0 0
30 31
0 0
1243/2058
1292