Register Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Address offset
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C -
0x3FFF
39.3.2

Register descriptions

The following sections detail the individual registers within the STM programming model.
39.3.2.1 STM Control Register (STM_CR)
The STM Control Register (STM_CR) includes the prescale value, freeze control and timer
enable bits.
Offset: 0x000
0 1
R 0 0
W
Reset 0 0
16 17
R
W
Reset 0 0
Table 434. STM memory map(Continued)
STM Channel 0 Control Register (STM_CCR0)
STM Channel 0 Interrupt Register (STM_CIR0)
STM Channel 0 Compare Register (STM_CMP0)
Reserved
STM Channel 1 Control Register (STM_CCR1)
STM Channel 1 Interrupt Register (STM_CIR1)
STM Channel 1 Compare Register (STM_CMP1)
Reserved
STM Channel 2 Control Register (STM_CCR2)
STM Channel 2 Interrupt Register (STM_CIR2)
STM Channel 2 Compare Register (STM_CMP2)
Reserved
STM Channel 3 Control Register (STM_CCR3)
STM Channel 3 Interrupt Register (STM_CIR3)
STM Channel 3 Compare Register (STM_CMP3)
Reserved
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
CPS
0 0 0 0
Figure 379. STM Control Register (STM_CR)
DocID027809 Rev 4
Register
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0
0 0 0 0
System Timer Module (STM)
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Access: Read/Write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
0 0 0 0
Location
14 15
0 0
0 0
30 31
FRZ TEN
0 0
847/2058
850