Table 143. Smpu0_Cesr1 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

System Memory Protection Unit (SMPU)
16.4.2.2 Control/Error Status Register 1 (SMPU0_CESR1)
Address SMPU0_CESR1 – FC01_0000h base + 4h offset = FC01_0004h
0 1
R
W
Reset 0 0
16 17
R 1
W
Reset 1 0
Figure 85. Control/Error Status Register 1 (SMPU0_CESR1)
Field
Master n error overrun, where the bus master number matches the bit number
Each bit in this field signals that another SMPU error for bus master n has occurred before the
previous error was processed. The details of the first error are recorded in the EARn and EDRn
0–15
registers, and no information on subsequent errors is recorded until the associated CESR0[MERR]
MEOVR
flag is cleared.
0 No error overrun condition has been detected for bus master n.
1 An error overrun condition has been detected for bus master n.
16
This read-only bit is reserved and always has the value '1'.
Reserved
17–27
This read-only bitfield is reserved and always has the value '0'.
Reserved
Number of region descriptors
Indicates the number of region descriptors implemented in the SMPU.
0001 4 region descriptors
28–31
0010 8 region descriptors
NRGD
0011 12 region descriptors
0100 16 region descriptors
0101 20 region descriptors
0110 24 region descriptors
16.4.2.3 Error Address Register, Bus Master n (SMPU0_EARn)
When the SMPU detects an access error on bus master n, the 32-bit reference address is
captured in this read-only register and the corresponding bit in CESR0[MERR] is set.
Additional information about the faulting access is captured in the corresponding EDRn at
the same time.
Note: The corresponding EARn and EDRn registers contain information on the original access
error; subsequent errors associated with the given master are recorded as overruns in the
CESR1[MEOVR] field until the original error is processed.
332/2058
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0

Table 143. SMPU0_CESR1 field descriptions

DocID027809 Rev 4
6 7 8 9
MEOVR
0 0 0 0
22 23 24 25
0
0 0 0 0
Description
Access: Supervisor read-only
10 11 12 13
0 0 0 0
26 27 28 29
NRGD
0 0 0 0
RM0400
14 15
0 0
30 31
X X