Functional Description; Interrupt Request Sources - STMicroelectronics SPC572L series Reference Manual

RM0400
18.6

Functional description

The functional description involves the areas of interrupt request sources, priority
management, and handshaking with the processor. In addition, spaces in the memory map
have been reserved for other possible implementations of the INTC.
18.6.1

Interrupt request sources

The INTC has two types of interrupt requests, peripheral and software-settable. These
interrupt requests can assert on any clock cycle.
The INTC has no spurious vector support. Therefore, if an asserted peripheral or software-
settable interrupt request, whose PRIn value in INTC_PSRn is higher than the PRI value in
INTC_CPRn, negates before the interrupt request to the processor for that peripheral or
software-settable interrupt request is acknowledged, then the interrupt request to the
processor still can assert (or will remain asserted) for that peripheral or software-settable
interrupt request. In this case, the interrupt vector will correspond to that peripheral or
software-settable interrupt request. Also, the PRI value in the associated INTC_CPRn is
updated with the corresponding PRIn value in INTC_PSRn.
Furthermore, clearing the peripheral interrupt request's enable bit in the peripheral, or
(alternatively) setting its mask bit, has the same consequences as clearing its flag bit.
Setting its enable bit or clearing its mask bit while its flag bit is asserted has the same effect
on the INTC as an interrupt event setting the flag bit.
18.6.1.1 Peripheral interrupt requests
An interrupt event in a peripheral's hardware sets a flag bit which resides in that peripheral.
The interrupt request from the peripheral is driven by that flag bit.
The time from when the peripheral starts to drive its peripheral interrupt request to the INTC,
to the time that the INTC starts to drive the interrupt request to the processor, is three
clocks.
18.6.1.2 Software-settable interrupt requests
The software set/clear interrupt registers (INTC_SSCIRn) support the setting or clearing of
software-settable interrupt requests. These registers contain independent sets of bits to set
and clear a corresponding flag bit by software. An interrupt request is triggered by software
by writing a 1 to a SET bit in INTC_SSCIRn. This write sets the corresponding CLR bit,
which is a flag bit, resulting in the interrupt request. The interrupt request is cleared by
writing a 1 to the CLR bit. Specific behavior includes the following:
•
Writing a 1 to SET leaves SET unchanged at 0 but sets the flag bit (which is the CLR
bit).
•
Writing a 0 to SET has no effect.
•
Writing a 1 to CLR clears the flag (CLR) bit.
•
Writing a 0 to CLR has no effect.
•
If a 1 is written to a pair of SET and CLR bits at the same time, the flag (CLR) is set,
regardless of whether CLR was asserted before the write.
The time from the write to the SET bit, to the time that the INTC starts to drive the interrupt
request to the processor, is four clocks.
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