Table 454. Pitx_Tctrln Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
0–28
This read-only bitfield is reserved and always has the value zero.
Reserved
Chain Mode Bit
When activated, timer n-1 needs to expire before timer n can decrement by 1.
29
Timer 0 cannot be changed.
CHN
0 Timer is not chained.
1 Timer is chained to previous timer (example, for channel 2 if this bit is set timer2 is chained 1).
Timer Interrupt Enable Bit
0 Interrupt requests from Timer n are disabled.
30
1 Interrupt will be requested whenever TIF is set.
TIE
When an interrupt is pending (TIF set), enabling the interrupt will immediately cause an interrupt
event. To avoid this, the associated TIF flag must be cleared first.
Timer Enable Bit
31
This bit enables or disables the timer.
TEN
0 Timer n is disabled.
1 Timer n is active.
41.2.1.7 PIT Module x Timer Flag Register n (PITx_TFLGn)
Address: Base + 0x010C
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Field
0–30
This read-only bitfield is reserved and always has the value zero.
Reserved
Timer Interrupt Flag
TIF is set to 1 at the end of the timer period. This flag can be cleared only by writing it with 1.
31
Writing 0 has no effect. If enabled (TIE = 1), TIF causes an interrupt request.
TIF
0 Timeout has not yet occurred.
1 Timeout has occurred.

Table 454. PITx_TCTRLn field descriptions

2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 399. Timer Flag Register n (PITx_TFLGn)
Table 455. PITx_TFLGn field descriptions
DocID027809 Rev 4
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Description
Periodic Interrupt Timer (PIT)
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
0 0 0 0
14 15
0 0
0 0
30 31
0 TIF
w1c
0 0
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