Machine State Register (Msr) - STMicroelectronics SPC572L series Reference Manual

RM0400
Bit(s) Name
30 —
31 —
12.6.2

Machine State Register (MSR)

The Machine State Register defines the state of the processor. The e200z215An3 MSR is
shown in
0
0 1 2 3 4 5 6
The MSR bits are defined in
Bit(s) Name
0:5 — Reserved
SP/Embedded FP/Vector available
0 SP/Embedded FP Double/The processor cannot execute SP/Embedded FP Double or
1 SP/Embedded FP Double/The processor can execute SP/Embedded FP Double or Vector
6 SPV
Note: For Zen z215An3, these units are not supported in hardware, and an illegal instruction
7:12 — Reserved
Wait State (Power management) enable
Note: This bit is implementation dependent and is being phased out. It is to be removed in
13 WE
Critical Interrupt Enable
14 CE
0 Critical Input interrupts are disabled.
1 Critical Input interrupts are enabled.
15 — Reserved
External Interrupt Enable
16 EE
0 External Input interrupts are disabled.
1 External Input interrupts are enabled.
Problem State
0 The processor is in supervisor mode, can execute any instruction, and can access any
17 PR
1 The processor is in user mode, cannot execute any privileged instruction, and cannot access
Table 95. ESR field descriptions(Continued)
Description
Reserved
Reserved
Figure 50.
0
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Read/ Write; Reset: 0x0
Figure 50. Machine State Register (MSR)
Table
Table 96. MSR field descriptions
Vector Unit instructions.
Unit instructions.
exception will be generated for attempted execution of these instructions regardless of
the setting of SPV. SPV is ignored, but cleared on exceptions.
future release. Currently, it is implemented as a writeable bit, and is ignored, but cleared
on exceptions.
resource (e.g. GPRs, SPRs, MSR, etc.).
any privileged resource.
DocID027809 Rev 4
0
96.
Description
Core e200z215An3 description
Associated interrupt type
—
—
0 0 0 0
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