Channel N Priority Register (Dma_Dchprin) - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Hardware request status channel 1
30
0 A hardware service request for the corresponding channel is not present
HRS1
1 A hardware service request for the corresponding channel is present
Hardware request status channel 0
31
0 A hardware service request for the corresponding channel is not present
HRS0
1 A hardware service request for the corresponding channel is present
19.3.16

Channel n Priority Register (DMA_DCHPRIn)

When the Fixed-Priority Channel Arbitration mode is enabled (CR[ERCA] = 0), the contents
of these registers define the unique priorities associated with each channel within a group.
The channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1
is the next higher priority, then 2, 3, and so on. Software must program the channel priorities
with unique values. Otherwise, a configuration error is reported. The range of the priority
value is limited to the values of 0 through 15.
Address: FC0A_0000h base + 100h offset + (1d × n), where n = 0d to 63d
0
R
ECP
W
(1)
Reset 0
1. x = Undefined at reset.
19.3.17 Channel n Master ID Register (DMA_DCHMIDn)
Field
Enable channel preemption
0
This bit resets to zero.
ECP
0 Channel n cannot be suspended by a higher priority channel's service request
1 Channel n can be temporarily suspended by the service request of a higher priority channel
Disable preempt ability
1
This bit resets to zero.
DPA
0 Channel n can suspend a lower priority channel
1 Channel n cannot suspend any channel, regardless of channel priority
Channel n arbitration priority
Channel priority when fixed-priority arbitration is enabled
4–7
Note: Reset value for the group and channel priority fields, GRPPRI and CHPRI, is equal to the
CHPRI
The DMA Master ID Replication registers allow the DMA to use the same protection level
and AHB system bus ID of the master programming the DMA's TCD. When enabled, the
Table 179. DMA_HRSL field descriptions(Continued)
1 2
0
DPA
0 x
Figure 134. Channel n Priority Register (DMA_DCHPRIn)
Table 180. DMA_DCHPRIn field descriptions
corresponding channel number for each priority register, i.e., DCHPRI31[GRPPRI] = 0b01
and DCHPRI31[CHPRI] equals 0b1111.
DocID027809 Rev 4
Enhanced Direct Memory Access (eDMA)
Description
3 4
0
x x
Description
Access: User read/write
5 6
CHPRI
x x
7
x
415/2058
449