Table 105. Program Interrupt—Register Settings - STMicroelectronics SPC572L series Reference Manual

Core e200z215An3 description
12.6.5.7 Program Interrupt (offset 0x60)
A program interrupt occurs when no higher priority exception exists and one or more of the
following exception conditions occur:
•
Illegal Instruction exception
•
Privileged Instruction exception
•
Trap exception
The e200z215An3 will invoke an Illegal Instruction program exception on attempted
execution of the following instructions:
•
Unimplemented instructions
•
An instruction from the illegal instruction class
•
mtspr and mfspr instructions with an undefined SPR specified
•
mtdcr and mfdcr instructions with an undefined DCR specified
The e200z215An3 will invoke a Privileged Instruction program exception on attempted
execution of the following instructions when MSR
•
A privileged instruction
• mtspr and mfspr instructions that specify a SPRN value with SPRN
SPR is undefined)
The e200z215An3 will invoke an Trap exception on execution of the tw instruction if the trap
conditions are met and the exception is not also enabled as a Debug interrupt.
The core will invoke an Illegal instruction program exception on attempted execution of the
instructions lswi, lswx, stswi, stswx, mfapidi, mfdcrx, mtdcrx, or on any PowerISA 2.06
floating-point instruction. All other defined or allocated instructions that are not implemented
by core will cause an illegal instruction program exception.
Table 105
Register
SRR0 Set to the effective address of the excepting instruction.
SRR1 Set to the contents of the MSR at the time of the interrupt
SPV 0
WE 0
MSR CE —
EE 0
PR 0
Illegal, Unimplemented:
ESR Privileged:
Trap:
MCSR Unchanged
DEAR Unchanged
Vector IVPR || 0x60
0:23
278/2058
lists register settings when a Program interrupt is taken.
Table 105. Program Interrupt—register settings
FP
ME
FE0
DE
PIL, VLEMI. All other bits cleared.
PPR, VLEMI. All other bits cleared.
PTR, VLEMI. All other bits cleared.
DocID027809 Rev 4
1 (user mode):
=
PR
Setting description
0
—
0
—
1 (even if the
=
5
FE1 0
IS 0
DS 0
PMM 0
RI —
RM0400