STMicroelectronics SPC572L series Reference Manual page 434

Enhanced Direct Memory Access (eDMA)
All channel priority levels within a group must be unique and all group priority levels
among the groups must be unique when Fixed Arbitration mode is enabled.
•
If a scatter/gather operation is enabled upon channel completion, a configuration error
is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32-byte
boundary.
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If minor loop channel linking is enabled upon channel completion, a configuration error
is reported when the link is attempted if the TCDn_CITER[E_LINK] bit does not equal
the TCDn_BITER[E_LINK] bit.
If enabled, all configuration error conditions, except the scatter/gather and minor-loop link
errors, report as the channel activates and asserts an error interrupt request. A
scatter/gather configuration error is reported when the scatter/gather operation begins at
major loop completion when properly enabled. A minor loop channel link configuration error
is reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is stopped and the
appropriate bus error flag set. In this case, the state of the channel's transfer control
descriptor is updated by the eDMA engine with the current source address, destination
address, and current iteration count at the point of the fault. When a system-bus error
occurs, the channel terminates after the read or write transaction (which is already pipelined
after errant access) has completed. If a bus error occurs on the last read prior to beginning
the write sequence, the write executes using the data captured during the bus error. If a bus
error occurs on the last write prior to switching to the next read sequence, the read
sequence executes before the channel terminates due to the destination bus error.
If an uncorrectable ECC error occurs during a peripheral bus access, the access is
terminated with a bus error. The occurrence of an uncorrectable ECC error during an eDMA
engine read causes the eDMA engine to stop the active channel immediately. The ECC
error and channel number are recorded in the eDMA's Error Status register.
A transfer may be cancelled by software with the CR[CX] bit. When a cancel transfer
request is recognized, the DMA engine stops processing the channel. The current read-
write sequence is allowed to finish. If the cancel occurs on the last read-write sequence of a
major or minor loop, the cancel request is discarded and the channel retires normally.
The error cancel transfer is the same as a cancel transfer except the ES register is updated
with the cancelled channel number and ECX is set. The TCD of a cancelled channel
contains the source and destination addresses of the last transfer saved in the TCD. If the
channel needs to be restarted, you must re-initialize the TCD since the aforementioned
fields no longer represent the original parameters. When a transfer is cancelled by the error
cancel transfer mechanism, the channel number is loaded into DMA_ES[ERRCHN] and
ECX and VLD are set. In addition, an error interrupt may be generated if enabled.
The occurrence of any error causes the eDMA engine to stop the active channel
immediately, and the appropriate channel bit in the eDMA error register is asserted. At the
same time, the details of the error condition are loaded into the ES register. The major loop
complete indicators, setting the transfer control descriptor DONE flag and the possible
assertion of an interrupt request, are not affected when an error is detected. After the error
status has been updated, the eDMA engine continues operating by servicing the next
appropriate channel. A channel that experiences an error condition is not automatically
disabled. If a channel is terminated by an error and then issues another service request
before the error is fixed, that channel executes and terminates with the same error
condition.
434/2058 DocID027809 Rev 4
RM0400