Decimation Filter
0
1
R
0
MDIS
W
1
Reset —
0
0
16
17
18
R
IDIS
SAT ISEL
W
Reset
1
0
0
1
Reset value is defined by the MDIS_DEFAULT parameter value.
Figure 360. Decimation Filter Module Configuration Register (DECFILTER_MCR)
Field
Module Disable
The MDIS bit puts the Decimation Filter in low power mode. Communication through the slave-
bus Interface is ignored in this mode. Writes to the configuration register are allowed with the
0
exception of writes to the FREN and SRES bits, which are ignored. Writes to the Coefficient
registers are also allowed. The Decimation Filter cannot enter Freeze mode once in disable
MDIS
mode. Once the module is disabled it no longer receives the system clock .
1 Low Power Mode
0 Normal Mode
Freeze Enable
The FREN bit enables the Decimation Filter to enter freeze mode if the SoC debug requestsignal or
1
the FRZ bit is asserted. See
FREN
1 Decimation Filter Freeze mode enabled
0 Decimation Filter Freeze mode disabled
2
Reserved
Freeze Mode
The FRZ bit controls the freeze mode of the Decimation Filter. For this bit to take effect the FREN
3
freeze enable bit also needs to be asserted. While in freeze mode the MAC operations are
halted. See
FRZ
1 Decimation Filter in Freeze Mode
0 Decimation Filter in Normal Mode
Software-reset bit
The SRES is a self-negated bit which provides the CPU with the capability to initialize the
4
Decimation Filter through the slave-bus interface. This bit always reads as zero. See
Section 37.4.9: Soft reset command
SRES
1 Software-Reset
0 No action
5-6
Reserved
810/2058
2
3
4
5
0
0
FRZ
0
0
0
19
20
21
0
DEC_RATE[3:0]
0
0
0
Table 420. DECFILTER_MCR field descriptions
Section 37.4.12: Freeze mode
Section 37.4.12: Freeze mode
Address: DECFILTER_BASE + 0x000
6
7
8
9
0
IDEN
0
0
0
0
22
23
24
25
SDIE
0
0
0
0
Description
description, for more details.
description, for more details.
DocID027809 Rev 4
Access: User read/write
10
11
12
13
0
0
FTYPE[1:0]
0
0
0
0
26
27
28
29
0
0
IBIE OBIE
0
0
0
0
description, for more details.
RM0400
14
15
SCAL[1:0]
0
0
30
31
0
0
0
0
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