Table 121. Siul2_Ifer0 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Address: 0x0038
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Figure 61. SIUL2 Interrupt Filter Enable Register 0 (SIUL2_IFER0)
Field
0–20 Reserved
Enable digital glitch filter on the interrupt pad input.
21
0 Filter is disabled
IFE10
1 Filter is enabled
22–25 Reserved
Enable digital glitch filter on the interrupt pad input.
26
0 Filter is disabled
IFE5
1 Filter is enabled
27 Reserved
28–31
IFE3
Enable digital glitch filter on the interrupt pad input.
IFE2
0 Filter is disabled
1 Filter is enabled
IFE1
IFE0
13.2.2.9 SIUL2 Interrupt Filter Maximum Counter Register (SIUL2_IFMCR0–
SIUL2_IFMCR31)
These registers are used to configure the filter counter associated with each digital glitch
filter.
Address: 0x0040 – 0x00BC
0 1 2 3 4
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXCNT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 62. SIUL2 Interrupt Filter Maximum Counter Register (SIUL2_IFMCR0)
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0
IFE1
0
0 0 0 0

Table 121. SIUL2_IFER0 field descriptions

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DocID027809 Rev 4
System Integration Unit Lite2 (SIUL2)
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Description
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0
IFE5 IFE3 IFE2 IFE1 IFE0
0 0 0 0
Access: User read/write
14 15
0 0
0 0
30 31
0 0
[3:0]
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