Register Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Offset
(hex)
3B Counter Compare 5 (CCMP5)
3C Counter Compare 6 (CCMP6)
3D Counter Compare 7 (CCMP7)
3E Counter Compare 8 (CCMP8)
3F Counter Compare 9 (CCMP9)
40 Counter Compare 10 (CCMP10)
41 Counter Compare 11 (CCMP11)
42 Counter Compare 12 (CCMP12)
43 Counter Compare 13 (CCMP13)
44 Counter Compare 14 (CCMP14)
45 Counter Compare 15 (CCMP15)
46 Counter Compare Status (CCOMS)
47 Counter Overflow Status (COS)
48 Counter Capture Status (CCAPS)
63.5.1

Register descriptions

63.5.1.1 Level1 input Mux configurations registers
A set of input Mux control registers is used to narrow down the large number of SPU
watchpoints to a manageable set. There are sixty-four 8 × 1 (eight inputs and one output)
multiplexers. Three bits per Mux are used to select one input out of 8 inputs. 8 Muxes are
configured with each 32-bit register; in other words, 8 inputs out of 64 for each register. This
provides the flexibility to the programmer to route any input trigger to any state input. The
detail of this selection is shown in
Note: Users cannot program MUX 63 in L1SEL7 (the 64
are tied to high and the output is always high (1'b1).
63.5.1.1.1 Level1 Mux Selection 0 (L1SEL0)
Figure 1064
L1SEL0 register are device dependent. For a description of these fields, see the device-
specific chapter that describes how the modules are configured.
Offset: 0x01
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0
MUX 7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 1015. SPU register summary(Continued)
Register
shows the format of the L1SEL0 register. The values for the fields of the
0 0
MUX 6 MUX 5
Figure 1064. L1SEL0 register format
DocID027809 Rev 4
Access
Figure 1097.
th
mux). All eight inputs of the 63
0
MUX 4 MUX 3
Sequence Processing Unit (SPU)
Reset
Value
R/W 32'h0 on page 1852
R/W 32'h0 on page 1852
R/W 32'h0 on page 1852
R/W 32'h0 on page 1852
R/W 32'h0 on page 1852
R/W 32'h0 on page 1852
R/W 32'h0 on page 1852
R/W 32'h0 on page 1852
R/W 32'h0 on page 1852
R/W 32'h0 on page 1852
R/W 32'h0 on page 1852
R/W 32'h0 on page 1852
R/W 32'h0 on page 1853
R/W 32'h0 on page 1854
Access: User read/write
8 7 6 5
0 0
MUX 2 MUX 1
Location
rd
mux
4 3 2 1 0
0
MUX 0
1825/2058
1863