Configuration/Debug Interface Jtag (1149.1) - STMicroelectronics SPC572L series Reference Manual

Nexus Aurora Router (NAR)
For example, the following steps can be used to generate event at around 90% fill level for
trace memory connected in AHB-EW and to set the watermark in the configuration register.
•
From the configuration, the programmer knows the following:
–
–
–
• Thus, the total block size is (0xC0 × 0x40) = 0x3000 bytes. The dedicated debug
address range is then 0x0D00_0000 – 0x0D00_2FFF.
•
To generate an event at nearly 90% fill level of the trace memory at 1 KB boundary, the
value to be programmed in the register NAR_AHFPAR[3:0] is calculated as:
–
–
•
NAR_AHFPAR[3:0] = (NAR_TBALO[13:10] + 0xB) = (0x7+0xB) 0x2 (upper bits
truncated due to width) and enable this with NAR_AHFPAR[10] = 1.
This assumes that NAR starts writing from base address and stops at maximum address
and no reading is done in overlay memory trace data area during this operation. Whenever
the address bus bits [13:10] match with this value, the partial event is generated (toggled).
65.5.13

Configuration/debug interface JTAG (1149.1)

The configuration and status registers of the NAR are accessed through the standard IEEE
1149.1 JTAG interface. The JTAG frequency (TCK) must be 1/2 of the NAR operating clock.
The access mechanism through JTAG is described in this section.
The NAR block uses the IEEE 1149.1-2001 TAP for accessing registers. TAP signals
include TCK, TDI, TMS, and TDO. The NAR implements a TAP controller state machine that
transitions based on the state of the IEEE 1149.1-2001 16-state state machine. It also
implements Nexus controller state machine as defined by the IEEE-ISTO 5001-2001
standard.
The instructions implemented by the NAR TAP controller are listed in
unimplemented instruction acts like the BYPASS instruction. The size of the NAR instruction
register is 4 bits.
1902/2058
AHB start (base) address—Base address = 0x0D00_0000 (i.e.TBAHI = 0x0,
TBALO = 0x0D00_0000
Block transfer size—NAR_TCR[BTM] = 1 (Block-transfer mode enabled)
Max transfer count—NAR_TCR[MXFR] = 0xC0 (maximum transaction count)
Number of 1K blocks in 0x3000 bytes = (3000 right shift by 10 bits) = C = 12
So the value to be programmed should be 11 as 90% of 12 is almost 11.
DocID027809 Rev 4
RM0400
Table 1067. Each