Protection Strategy - STMicroelectronics SPC572L series Reference Manual

RM0400
While UT0[AID] is low and UT0[AIE] is high, the user may abort Margin Read by clearing
AIE. UT0[AID] must be checked to know when the aborting command has completed.
Margin Read can be suspended by setting UT0[AISUS] while Margin Read is running
(UT0[AID]=0). Once suspended (UT0[AID]=1), Margin Read cannot be aborted and clearing
UT0[AISUS] starts the Resume.
UM0/9 = 0x0000_0000;/* Reset UM0/9 content */
UT0 = 0xF9F9_9999;/* Set UTE in UT0: Enable User Test */
SEL0 = 0x0006_0000;/* Set LSL2-1 in SEL0: Select Blocks */
UT0 = 0x8000_0020;/* Set MRE in UT0: Select Operation */
UT0 = 0x8000_0030;/* Set MRV: Select Margin versus 1's */
UT0 = 0x8000_0032;/* Set AIE in UT0: Operation Start */
do
{ tmp = UT0;
} while ( !(tmp & 0x0000_0001) );
data0/9= UM0/9;/* Read UM0/9 content*/
UT0 = 0x8000_0030;/* Reset AIE in UT0: Operation End */
UT0 = 0x0000_0000;/* Reset UTE, MRE, MRV, AIS in UT0:
29.4.6

Protection strategy

Two kinds of protection are available: Modify Protection to avoid unwanted program/erase in
flash blocks and Test Mode Disable to avoid piracy.
29.4.6.1 Modify Protection
The Flash Modify Protection information is stored in nonvolatile flash cells located in the
UTEST region. This information is read once during the Flash Initialization phase following
exit from reset and is stored in volatile registers that act as actuators at SoC level. The
information is passed to the Flash Memory module through erase_lock and program_lock
sidebands, and allows independent protection of each block of Low, Mid, High and 256K
Address Space Block.
There are also Address Space Block Locking registers provided to independently
lock/unlock each block of Low, Mid, High and 256K Address Space Block against program
and erase. Locking is done through the LOCK0, LOCK1, and LOCK2 registers. These
registers do not have a nonvolatile image stored in the UTEST area of TestFlash, so the
locking information is kept on reset: volatile content is all 1's, meaning all blocks are locked.
All the volatile registers can be written to '0' or '1' at any time, therefore the user application
can lock and unlock blocks when desired. Note, however, that overall protection is achieved
by the combination of sidebands with Low, Mid, High and 256K Address Space Block
Locking registers in such a way that a block can be programmed/erased only if both
(sidebands and Locking registers) indicate an unlocked state. Sidebands independently
control program protection, erase protection and over-programming protection (OPP) on a
block-by-block basis.
As UTEST and BAF (each one with its own lock bit, LOCK0[TSLOCK] and
LOCK0[LOWLOCK] respectively) are two sections of the same physical block (TestFlash),
effective locking is achieved via the 'AND' operand of the lock bits. For effective locking,
Example 11. Margin Read Check versus 1's
/* Loop to wait for AID=1 */
/* Read UT0 */
Deselect Operation */
DocID027809 Rev 4
Embedded Flash Memory (MP55)
643/2058
644