Table 1023. Ioicn Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
unused if not required for that state by selecting 000000 (No input selected option) in the
L2nSEL registers. The output of each AND gate has the optional inversion control as well.
The output can be routed directly or with inversion from each AND gate to the input of OR
gate. Figure 1081
0x37 (State0)
0x38 (State1)
0x39 (State2)
0x3A (State3)
Offset
0x3B (State4)
0x3C (State5)
0x3D (State6)
0x3E (State7)
31 30 29 28 27 26 25
R 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0
15 14 13 12 11 10 9
R 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0
The IOICn register fields are described in
Field
Input 1 AND Gate 1 Control.
0
0 Input 1 is used directly (without inversion) for this event
InAND1
1 Input 1 is inverted for this event
Input 1 AND Gate 2 Control.
1
0 Input 1 is used directly (without inversion) for this event
InAND2
1 Input 1 is inverted for this event
Input 1 AND Gate 3 Control.
2
0 Input 1 is used directly (without inversion) for this event
InAND3
1 Input 1 is inverted for this event
Input 1 AND Gate 4 Control.
3
0 Input 1 is used directly (without inversion) for this event
InAND4
1 Input 1 is inverted for this event
Output AND Gate 1 Control.
4
0 Output is used directly (without inversion) for this event
OutAND1
1 Output is inverted for this event
Output AND Gate 2 Control.
5
0 Output is used directly (without inversion) for this event
OutAND2
1 Output is inverted for this event
shows the format of the IOICn register where the state number, n = 0–7.
24 23 22
0 0 0
0 0 0
8 7 6
OutOR OutAND4 OutAND3 OutAND2 OutAND1
0 0 0
Figure 1081. IOICn register format

Table 1023. IOICn register field descriptions

DocID027809 Rev 4
Sequence Processing Unit (SPU)
21 20
0 0
0 0
5 4
0 0
Table 1023.
Description
Access: User read/write
19 18 17
0 0 0
0 0 0
3 2 1
InAND InAND InAND
4 3 2
0 0 0
16
0
0
0
InAND1
0
1837/2058
1863