Table 957. Ocmd Field Descriptions - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
R/W GO
0 1
Reset - 10'b1000000010 on assertion of j_trst_b or m_por, or while in the Test_Logic_Reset state
Table 957
Bit Name
Read/Write Command Bit
The R/W bit specifies the direction of data transfer. The table below describes the options
defined by the R/W bit.
Note: The R/W bit generally ignored for read-only or write-only registers, although the PC
0 R/W
0 Write the data associated with the command into the register specified by RS[0:6]
1 Read the data contained in the register specified by RS[0:6]
Go Command Bit
If the GO bit is set, and the CPU is currently in debug mode, the CPU will execute the
instruction that resides in the IR register in the CPUSCR. To execute the instruction, the
processor leaves the debug mode, executes the instruction, and if the EX bit is cleared,
returns to the debug mode immediately after executing the instruction. The processor goes
on to normal operation if the EX bit is set, and no other debug request source is asserted.
The GO command is executed only if the operation is a read/write to CPUSCR or a
read/write to "No Register Selected". Otherwise the GO bit is ignored.The processor will
leave the debug mode after the TAP controller Update-DR state is entered.
On a GO+NoExit operation, returning to debug mode is treated as a debug event, thus
exceptions such as machine checks and interrupts may take priority and prevent execution
1 GO
of the intended instruction. Debug firmware should mask these exceptions as appropriate.
The OSR
If the CPU is not currently in debug mode, then the GO command will be ignored.
Note: Asynchronous interrupts are blocked on a GO+Exit operation until the first instruction
0 Inactive (no action taken)
1 Execute instruction in IR
1702/2058
EX
2 3
Figure 1009. OnCE Command (OCMD) register
provides bit definitions for the OCMD.

Table 957. OCMD field descriptions

FIFO pointer is only guaranteed to be update when R/W=1. In addition, it is ignored for
all bypass operations. When performing writes, most registers are sampled in the
Capture-DR state into a 32-bit shift register, and subsequently shifted out on j_tdo
during the first 32 clocks of Shift-DR.
bit indicates such an occurrence.
ERR
to be executed begins execution. See
interrupt blocking.
DocID027809 Rev 4
RS[0:6]
4 5 6
Description
Section 57.5.9.6, Exiting Debug mode and
RM0400
7 8 9