Figure 980. Core Status Register (Me_Cs) - STMicroelectronics SPC572L series Reference Manual

Mode Entry Module (MC_ME)
Table 932. Peripheral Control Registers (ME_PCTLn) field descriptions(Continued)
Field
Peripheral configuration select for non-run modes — These bits associate a configuration as defined
in the ME_LP_PC0
000 Selects ME_LP_PC0 configuration
001 Selects ME_LP_PC1 configuration
2–4
010 Selects ME_LP_PC2 configuration
LP_CFG 011 Selects ME_LP_PC3 configuration
100 Selects ME_LP_PC4 configuration
101 Selects ME_LP_PC5 configuration
110 Selects ME_LP_PC6 configuration
111 Selects ME_LP_PC7 configuration
Peripheral configuration select for run modes — These bits associate a configuration as defined in
the ME_RUN_PC0
000 Selects ME_RUN_PC0 configuration
001 Selects ME_RUN_PC1 configuration
5–7
010 Selects ME_RUN_PC2 configuration
RUN_CFG 011 Selects ME_RUN_PC3 configuration
100 Selects ME_RUN_PC4 configuration
101 Selects ME_RUN_PC5 configuration
110 Selects ME_RUN_PC6 configuration
111 Selects ME_RUN_PC7 configuration
56.3.2.23 Core Status Register (ME_CS)
Address 0x1C0
0 1 2
R 0 0 0
W
Reset 0 0 0
16 17 18
R 0 0 0
W
Reset 0 0 0
This register provides the status of each core.
1626/2058
...
7 registers to the peripheral.
...
7 registers to the peripheral.
3 4 5 6
0 0 0 0
0 0 0 0
19 20 21 22
0 0 0 0
0 0 0 0

Figure 980. Core Status Register (ME_CS)

DocID027809 Rev 4
Description
Access: User read, Supervisor read, Test read
7 8 9 10
0 0 0 0
0 0 0 0
23 24 25 26
0 0 0 0
0 0 0 0
RM0400
11 12 13 14
0 0 0 0
0 0 0 0
27 28 29 30
0 0 0 0
0 0 0 0
15
0
0
31
0