Implementing Secure Write Protection - STMicroelectronics SPC572L series Reference Manual

RM0400
Password 0
PASS_LOCK0PG0
Password 1
PASS_LOCK0PG1
Password 2
PASS_LOCK0PG2
Password 3
PASS_LOCK0PG3
ORed write protection bits override settings
in FLASH_LOCKn registers
The next sections discuss implementing secure write protection and overriding secure write
protection.
31.3.1

Implementing secure write protection

Implementing secure write protection is a one-time task performed either at the factory or by
the customer during chip configuration activities. It normally requires creating a DCF record
for each of the PASS_LOCK0_PGn–PASS_LOCK2_PGn registers
have a structure that includes the same mapping of bits to flash memory blocks as the flash
module's SELn and LOCKn registers. The values assigned become the permanent register
reset values for the PASS_LOCK0_PGn–PASS_LOCK2_PGn registers.
See Chapter 8: Device Configuration Format (DCF) Records
records. This section summarizes the contents of a DCF record as required to implement
secure write protection.
Even though the mapping of bits to flash memory blocks is identical to the mapping used for
selecting flash blocks for erase of non-secure write locking, there are two significant
differences:
1. Configuring flash blocks for secure write protection is done only during device
configuration to customer specifications, either at the factory or by the customer during
i. The default behavior for secure write protection in the case where passwords are created but no secure write
protection DCF records are created, is for all blocks to have four levels of password-secured write protection.
To vary the protection among all blocks, a DCF record for each password group must be created.
Figure 288. Secure write protection
Flash memory block write-protection bits
PASS_LOCK1PG0
PASS_LOCK1PG1
PASS_LOCK1PG2
PASS_LOCK1PG3
OR OR
DocID027809 Rev 4
Flash Memory Programming and Configuration
Flash memory region
read-protection bits
and debug locking bits
PASS_LOCK2PG0 PASS_LOCK3PG0
PASS_LOCK2PG1 PASS_LOCK3PG1
PASS_LOCK2PG2 PASS_LOCK3PG2
PASS_LOCK2PG3 PASS_LOCK3PG3
OR OR
ORed RP bits control read
protection regions; ORed DBL
bits control debug access
(i)
. The DCF records
for complete details on DCF
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