Functional Description - STMicroelectronics SPC572L series Reference Manual

Clock Generation Module (MC_CGM)
Table 269. Auxiliary Clock 11 Divider 1 Configuration Register (CGM_AC11_DC1) field
Field
Divider Division Value — The resultant DSPI clock 1 will have a period 'DIV + 1' times that of auxiliary
12–15
clock 11. If DE is set to 0 (divider 0 is disabled), any write access to the DIV field is ignored and the DSPI
DIV
clock 1 remains disabled.
16–31 Reserved
24.4

Functional Description

24.4.1 System Clock Generation
Figure 213 shows the block diagram of the system clock generation logic. The MC_ME provides the
system clock select and switch mask (see MC_ME chapter for more details), and the MC_RGM provides
the safe clock request (see MC_RGM chapter for more details). The safe clock request forces the
selector to select the 16 MHz internal RC oscillator (IRCOSC) as the system clock and to ignore the
system clock select.
24.4.1.1 System Clock Source Selection
During normal operation, the system clock selection is controlled
•
on a SAFE mode or reset event, by the MC_RGM
•
otherwise, by the MC_ME
24.4.1.2 Progressive System Clock Switching
In order to prevent sudden voltage drops and overshoots due to frequency and load changes, the
MC_ME requests the MC_CGM to ramp the system clock frequency down and/or up based on the power
level values of the current and target modes. During ramp-down, the rate of the frequency change is
based on the CGM_PCS_SDUR, CGM_PCS_DIVCn, and CGM_PCS_DIVEn registers, where n
corresponds to the current system clock source selection. During ramp-up, the rate of the frequency
change is based on the CGM_PCS_SDUR, CGM_PCS_DIVCn, and CGM_PCS_DIVSn registers, where
n corresponds to the target system clock source selection.
24.4.1.2.1 Generic Clock Change Requirements
For a maximum allowed change of the frequency (f
(current or target clock source), the maximum allowed frequency change rate a
Equation 8
24.4.1.2.2 Configuration of CGM_PCS_SDUR
The switch duration field CGM_PCS_SDUR[SDUR] defines the duration of one system clock switch step
in terms of 16 MHz internal RC oscillator (IRCOSC). After the expiration of this time, the module changes
the clock divider value which chnages the frequency of the system clock.
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descriptions(Continued)
Description
) and for a given source clock frequency f
chg
f
chg
--------- -
a
=
max
f
src
DocID027809 Rev 4
RM0400
src
is given in Equation 8
max .