Table 1026. Ss Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Sequence Processing Unit (SPU)
Field
Next State on False Condition. Defines the Goto next state in case of false condition from the present
state. States may remain in the same state on a false condition if the same state is chosen as the next
state.
000 Goto State 0
001 Goto State 1
7–5
010 Goto State 2
NF
011 Goto State 3
100 Goto State 4
101 Goto State 5
110 Goto State 6
111 Goto State 7
31–8 Reserved. Read returns 0.
63.5.1.4 SLU status (SS) register
The SLU status register indicates the states that have been hit/encountered in any of the
active sequences.
Offset 0x48
31 30 29
R 0 0 0
W
Reset 0 0 0
15 14 13
R SAS3
W w1c w1c w1c
Reset 0 0 0
The SS register fields are described in
Field
State Hit 0. This bit is set when State0 is hit/encountered in any of the active sequences
0
0 State not hit
SH0
1 State hit
State Hit 1. This bit is set when State1 is hit/encountered in any of the active sequences
1
0 State not hit
SH1
1 State hit
State Hit 2. This bit is set when State2 is hit/encountered in any of the active sequences
2
0 State not hit
SH2
1 State hit
1842/2058
Table 1025. SnGC register field descriptions(Continued)
Figure 1084
28 27 26
0 0 0
0 0 0
12 11 10
SAS2 SAS1
w1c w1c w1c
0 0 0
Figure 1084. SS register format

Table 1026. SS register field descriptions

DocID027809 Rev 4
Description
shows the format of the SS register.
25 24 23 22
0 0 IM0 EM2
w1c w1c
0 0 0 0
9 8 7 6
SH7 SH6
w1c w1c w1c w1c
0 0 0 0
Table 1026.
Description
Access: User read/write
21 20 19 18
0 0 SAS4
w1c w1c
0 0 0 0
5 4 3 2
SH5 SH4 SH3 SH2
w1c w1c w1c w1c
0 0 0 0
RM0400
17 16
SAS3
w1c w1c
0 0
1 0
SH1 SH0
w1c w1c
0 0