Debug / Halt Mode Description - STMicroelectronics SPC572L series Reference Manual

RM0400
43.3.5

Debug / Halt Mode Description

The debug / halt mode is requested via GTMDI and is used to debug the GTM-IP sub-block.
In this mode it is required that the core of GTM-IP becomes halted by stopping its clock.
Therefore all time bases and counters are frozen.
Debug or halt mode requests should be enabled by setting the bit field DBE on the GTMDI
GTMDI_DC register that is accessible by the JTAG interface (refer to the GTMDI chapter for
more details). GTM halt is only activated when no read- or write-access to GTM over AEI
are taking place in parallel. Only in this condition the GTM is released to change to debug /
halt mode read.
It is important to notice that any slave bus access is active in this mode. Debugger is able to
read all GTM addresses read-/writeable from the peripheral bus when GTM is running or
halted. All registers in the register map can be accessed by the slave bus, even the RAMs
because they are in the register map. Of course, the clocks for the RAMs are not stopped in
debug mode.
For more details about the debug mode, please refer to GTMDI documentation.
Note: If this module is in disable mode by setting GTMMCR[MDIS], the debug request is not
considered until the MDIS bit is cleared.
43.3.6 GTM-IP Timer Software Reset Description
The GTM-IP timer portion has the software reset possibility by writing a '1' in the RST bit
field on the GTM_RST register. This bit is self cleared and is always read as zero. In
addition, this bit is write protected by the bit field RF_PROT in the GTM_CTRL register.
This is a global reset to GTM-IP block only. The GTMDI is not affected by this soft-reset.
43.3.7 AEI Interface Software Reset Description
The GTM-IP has software reset control for the AEI interface sub-block only. This block is the
slave bus interface of GTM-IP and is not reset by the GTM-IP timer soft-reset. The AEI soft-
reset occurs by writing a '1' in the field GTMMAEICR[AEISRST]. This bit is self cleared and
is always read as zero. In addition, this bit is write protected by the field
GTMMCR[AEISREN].
A soft-reset in the AEI interface is equivalent to the hard-reset. It occurs in the next clock
cycle of the request and takes one bus clock cycle. The AEI buffer and configuration
registers are cleared, and some slave bus access can be aborted. Therefore, access
commands in the buffer memory are lost and the configuration registers of the AEI interface
change to their reset values.
43.3.8 Interrupt and DMA Support Logic
The GTM-IP provides several interrupts / DMA request signals to signalize internal events to
other external modules. The list of all signals are provided in the GTM-IP documentation
and all have the same type of controls and configuration options.
Each interrupt / DMA request line represents a set of internal interrupt / DMA request
signals, and each of this internal signal has its own set of status / control / configuration
registers: IRQ_EN, IRQ_NOTIFY, IRQ_FORCINT, and IRQ_MODE registers. Please refer
to GTM-IP specification for more details.
GTM101 Integration (GTMINT) Module
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