Figure 648. Iclc Control Register (Icr) - STMicroelectronics SPC572L series Reference Manual

LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communications
Field
Wake Up time for the LD. Defines the 1/4 of the number of High speed clock cycles used during the
wakeup of the LD from shutdown mode. This is time required by the LD to move from moving from
Shutdown to Normal State in High speed mode.
00h0 cycles
16-23
01h1 cycle
HWKCNT
...
5Fh95 cycles (1.18 us)
...
FFh255 cycles Maximum
24-27 Reserved
Wake Up time for the LD. Defines the 1/4 of the number Low speed clock used during the wakeup of
the LD from shutdown mode. This is time required by the LD to move from Shutdown to Normal State
in Low speed mode.
0h0 cycle
28-31
1h1 cycle
LWKCNT
2h2 cycles (1.18 us)
...
Eh14 cycles
Fh15 cycles
47.6.2.8 ICLC Control Register (ICR)
Offset:
001Ch
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
1
Writable only when ICR[SNDICLC] = 0
2
Set by user software and cleared by system hardware.
1236/2058
Table 662. SLCR field descriptions(Continued)
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0

Figure 648. ICLC Control Register (ICR)

DocID027809 Rev 4
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0
0 0 0 0
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
1
ICLCPLD
0 0 0 0
14 15
0 0
30 31
0 0