Access Errors - STMicroelectronics SPC572L series Reference Manual

Register Protection (REG_PROT)
When writing to address 0x2008 the registers MR9 and MR8 in the protected module are
updated. The corresponding lock bits SLBR2.SLB[1:0] are set while the lock bits
SLBR2.SLB[3:2] remain unchanged (right part of
Figure 1196
Before write access
0 0 0 0 0 0 0 0
SLB[3:0]
WE[3:0]
In the example in
corresponding lock bits SLBR3.SLB[1:0] are always 0b0 (shown in bold). When doing a 32-
bit write access to address 0x200C only lock bits SLBR3.SLB[3:2] are set while bits
SLBR3.SLB[1:0] stay 0b0.
Note: Lock bits can only be set via writes to the mirror module space. Reads from the mirror
module space will not change the lock bits.
67.4.2.3 Write protection for locking bits
Changing the locking bits through any of the procedures mentioned in
Change lock settings directly via Area #4
module space (Area #3)
bit is set the locking bits can no longer be modified until there is a system reset.
67.4.3

Access errors

The protection module generates transfer errors under several circumstances. For the area
definition refer to
1. If accessing area #1 or area #3, the protection module will pass on any access error
from the underlying Module under Protection.
2. If user mode is not allowed, user writes to all areas will assert a transfer error and the
writes will be blocked.
3. If accessing the reserved area #2, a transfer error will be asserted.
4. If accessing unimplemented 32-bit registers in area #4 and area #5 a transfer error will
be asserted.
5. If writing to a register in area #1 and area #3 with Soft Lock Bit set for any of the
affected bytes a transfer error is asserted and the write will be blocked. Also the
complete write operation to non-protected bytes in this word is ignored.
6. If writing to a Soft Lock Register in area #4 with the Hard Lock Bit being set a transfer
error is asserted.
7. Any write operation in any access mode to area #3 while Hard Lock Bit GCR.HLB is set
1992/2058
shows an example where some addresses are protected and some are not:
Figure 1196. Enable locking for protected and unprotected addresses
After
SLBR3
write access
Figure 1196
is only possible as long as the bit GCR.HLB is cleared. Once this
Figure 1187
Figure
32-Bit write to address 0x200C
set lock bits
0 0 0 0 0 0 1 1
WE[3:0]
addresses 0x0C and 0x0D are unprotected. Therefore their
and Section 67.4.2.2, Enable locking via mirror
DocID027809 Rev 4
1192).
write to
SLBR3
SLB[3:0]
Section 67.4.2.1,
RM0400
MR[15:12]